Searched refs:RT_regw (Results 1 - 3 of 3) sorted by relevance

/xsrc/external/mit/xf86-video-ati/dist/src/
H A Dtheatre200.c139 #define RT_regw(reg,data) theatre_write(t,(reg),(data)) macro
370 RT_regw(VIP_HOSTINTF_PORT_CNTL, data & (~VIP_HOSTINTF_PORT_CNTL__FIFO_RW_MODE));
374 RT_regw(VIP_HOSTINTF_PORT_CNTL, data & (~VIP_HOSTINTF_PORT_CNTL__FIFOD_ENDIAN_SWAP));
424 RT_regw(VIP_TC_DOWNLOAD, (data & ~VIP_TC_DOWNLOAD__TC_RESET_MODE) | (0x02 << 17));
431 RT_regw(VIP_TC_SOURCE, 0x90000000);
432 RT_regw(VIP_TC_DESTINATION, 0x00000000);
433 RT_regw(VIP_TC_COMMAND, 0xe0000044 | ((seg_list->num_bytes - 1) << 7));
460 RT_regw(VIP_TC_SOURCE, 0x00000000);
461 RT_regw(VIP_TC_DESTINATION, 0x10000000);
462 RT_regw(VIP_TC_COMMAN
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H A Dtheatre.c28 #define RT_regw(reg,data) theatre_write(t,(reg),(data)) macro
607 if (RT_regw (RT_RegMap[dwReg].dwRegAddrLSBs, dwValue) == TRUE)
1885 RT_regw (VIP_PLL_CNTL1, data & ~((RT_VINRST_RESET << 1) | (RT_L54RST_RESET << 3)));
1890 RT_regw (VIP_CLOCK_SEL_CNTL, data | (RT_PLL_VIN_CLK << 7));
1895 RT_regw (VIP_HW_DEBUG, 0x0000F000);
1905 RT_regw (VIP_DVS_PORT_CTRL, data | RT_DVSDIR_OUT);
1910 RT_regw (VIP_ADC_CNTL, RT_ADC_CNTL_DEFAULT);
1915 RT_regw (VIP_MASTER_CNTL, data & ~0x20);
1920 RT_regw (VIP_MASTER_CNTL, data & ~(RT_DVS_ASYNC_RST));
1924 RT_regw (VIP_HS_GENLOCKDELA
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H A Dtheatre_detect.c78 #define RT_regw(reg,data) theatre_write(t,(reg),(data))

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