Searched refs:align_offset (Results 1 - 25 of 51) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/compiler/nir/
H A Dnir_lower_ubo_vec4.c94 unsigned align_offset = nir_intrinsic_align_offset(intr); local in function:nir_lower_ubo_vec4_lower
103 align_offset &= 15;
104 assert(align_offset % chan_size_bytes == 0);
108 align_offset + chan_size_bytes * num_components <= 16);
120 int align_chan_offset = align_offset / chan_size_bytes;
137 align_offset + chan_size_bytes * intr->num_components <= 8) {
H A Dnir_lower_io.c1198 uint32_t align_mul, uint32_t align_offset,
1208 align_mul, align_offset,
1216 align_mul, align_offset,
1222 align_mul, align_offset,
1233 align_mul, align_offset,
1240 align_mul, align_offset,
1377 nir_intrinsic_set_align(load, align_mul, align_offset);
1439 uint32_t align_mul, uint32_t align_offset,
1448 align_mul, align_offset,
1455 align_mul, align_offset,
1195 build_explicit_io_load(nir_builder * b,nir_intrinsic_instr * intrin,nir_ssa_def * addr,nir_address_format addr_format,nir_variable_mode modes,uint32_t align_mul,uint32_t align_offset,unsigned num_components) argument
1436 build_explicit_io_store(nir_builder * b,nir_intrinsic_instr * intrin,nir_ssa_def * addr,nir_address_format addr_format,nir_variable_mode modes,uint32_t align_mul,uint32_t align_offset,nir_ssa_def * value,nir_component_mask_t write_mask) argument
1770 uint32_t align_mul, align_offset; local in function:nir_lower_explicit_io_instr
1861 nir_get_explicit_deref_align(nir_deref_instr * deref,bool default_to_type_align,uint32_t * align_mul,uint32_t * align_offset) argument
[all...]
H A Dnir_opt_load_store_vectorize.c177 uint32_t align_offset; member in struct:entry
562 entry->align_offset = entry->offset % entry->align_mul;
565 entry->align_offset = nir_intrinsic_align_offset(entry->intrin);
664 low->align_offset,
805 first->align_offset = low->align_offset;
891 second->align_offset = low->align_offset;
1058 uint64_t max_low = round_down(UINT64_MAX, low->align_mul) + low->align_offset;
1170 entry->align_offset !
[all...]
H A Dnir_opt_large_constants.c89 .align_offset = 0);
H A Dnir_instr_set.c176 hash = HASH(hash, instr->cast.align_offset);
631 deref1->cast.align_offset != deref2->cast.align_offset)
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/etnaviv/tests/
H A Dlower_ubo_tests.cpp143 nir_load_ubo(&b, 1, 32, index, offset, .align_mul = 16, .align_offset = 0, .range_base = 0, .range = 8);
158 nir_load_ubo(&b, 1, 32, index, offset, .align_mul = 16, .align_offset = 0, .range_base = 0, .range = 8);
175 nir_load_ubo(&b, 1, 32, index, offset, .align_mul = 16, .align_offset = 0, .range_base = 0, .range = 8);
/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A Danv_nir_lower_ubo_loads.c98 .align_offset = nir_intrinsic_align_offset(load));
108 .align_offset = nir_intrinsic_align_offset(load));
H A Danv_nir_apply_pipeline_layout.c267 .align_offset = desc_offset % 8);
278 .align_offset = desc_offset % 8,
937 cast->cast.align_offset = 0;
943 cast->cast.align_offset = 0;
1106 .align_offset = 0,
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_acceleration_structure.c722 .align_mul = 2, .align_offset = 0);
730 b, 3, 32, nir_iadd(b, addr, nir_u2u64(b, index_id)), .align_mul = 4, .align_offset = 0);
751 .align_mul = 1, .align_offset = 0);
786 .align_mul = 4, .align_offset = 0),
805 .align_mul = comp_bytes, .align_offset = 0);
987 .align_mul = 4, .align_offset = 0),
992 .align_mul = 4, .align_offset = 0),
997 .align_mul = 4, .align_offset = 0),
1015 .write_mask = 15, .align_mul = 16, .align_offset = 0);
1020 .align_offset
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H A Dradv_pipeline_rt.c352 nir_build_load_global(b, 1, 32, load_addr, .align_mul = 4, .align_offset = 0);
397 .align_mul = 64, .align_offset = offset + i * 16);
638 .align_mul = 4, .align_offset = 0);
650 .align_mul = 64, .align_offset = 16),
654 .align_mul = 64, .align_offset = 32),
658 .align_mul = 64, .align_offset = 48)};
1267 .align_mul = 4, .align_offset = 0);
1372 b, 2, 32, nir_iadd(b, node_addr, nir_imm_int64(b, 24)), .align_mul = 4, .align_offset = 0);
1451 .align_mul = 4, .align_offset = 0);
1454 .align_mul = 4, .align_offset
[all...]
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/sfn/
H A Dsfn_instruction_export.h84 int align_offset, int writemask);
86 int align, int align_offset, int writemask, int array_size);
H A Dsfn_instruction_export.cpp104 int align, int align_offset, int writemask):
108 m_align_offset(align_offset),
115 int align, int align_offset, int writemask, int array_size):
120 m_align_offset(align_offset),
103 WriteScratchInstruction(unsigned loc,const GPRVector & value,int align,int align_offset,int writemask) argument
114 WriteScratchInstruction(const PValue & address,const GPRVector & value,int align,int align_offset,int writemask,int array_size) argument
/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_nir_lower_mem_access_bit_sizes.c170 const unsigned align_offset = nir_intrinsic_align_offset(intrin); local in function:lower_mem_store_bit_size
210 (align_mul >= 4 && (align_offset + start) % 4 == 0) ||
H A Dbrw_nir.c940 brw_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset, argument
962 if (align_offset)
963 align = 1 << (ffs(align_offset) - 1);
/xsrc/external/mit/MesaLib/dist/src/broadcom/vulkan/
H A Dv3dv_image.c214 uint32_t align_offset = local in function:v3d_setup_slices
216 if (align_offset) {
217 image->size += align_offset;
219 image->slices[i].offset += align_offset;
/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dbrw_nir_lower_mem_access_bit_sizes.c167 const unsigned align_offset = nir_intrinsic_align_offset(intrin); local in function:lower_mem_store_bit_size
202 (align_mul >= 4 && (align_offset + start) % 4 == 0) ||
/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_nir_lower_esgs_io_to_mem.c143 .align_mul = 16u, .align_offset = (nir_intrinsic_component(intrin) * 4u) % 16u);
217 .align_mul = 16u, .align_offset = (nir_intrinsic_component(intrin) * 4u) % 16u);
H A Dac_nir_lower_tess_io_to_mem.c226 .align_mul = 16u, .align_offset = (nir_intrinsic_component(intrin) * 4u) % 16u);
383 .align_mul = 16u, .align_offset = (nir_intrinsic_component(intrin) * 4u) % 16u);
421 .align_mul = 16u, .align_offset = (nir_intrinsic_component(intrin) * 4u) % 16u);
432 .align_mul = 16u, .align_offset = (nir_intrinsic_component(intrin) * 4u) % 16u);
523 .align_mul = 16u, .align_offset = st->tcs_tess_lvl_out_loc % 16u);
526 .align_mul = 16u, .align_offset = st->tcs_tess_lvl_in_loc % 16u)
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/virgl/
H A Dvirgl_resource.c274 unsigned align_offset; local in function:virgl_staging_map
294 * |---| ==> align_offset
295 * |------------| ==> allocation of size + align_offset
297 align_offset = vres->b.target == PIPE_BUFFER ?
302 virgl_staging_alloc(&vctx->staging, size + align_offset,
309 * if we have an align_offset (see above for more information). */
310 vtransfer->copy_src_offset += align_offset;
311 map_addr += align_offset;
327 vctx->queued_staging_res_size += size + align_offset;
/xsrc/external/mit/MesaLib.old/dist/src/compiler/nir/
H A Dnir.h1374 * (X - align_offset) % align_mul == 0
1492 INTRINSIC_IDX_ACCESSORS(align_offset, ALIGN_OFFSET, unsigned)
1497 unsigned align_mul, unsigned align_offset)
1500 assert(align_offset < align_mul);
1502 nir_intrinsic_set_align_offset(intrin, align_offset);
1516 const unsigned align_offset = nir_intrinsic_align_offset(intrin); local in function:nir_intrinsic_align
1517 assert(align_offset < align_mul);
1518 return align_offset ? 1 << (ffs(align_offset) - 1) : align_mul;
/xsrc/external/mit/MesaLib/dist/src/compiler/glsl/
H A Dgl_nir_lower_buffers.c240 cast->cast.align_offset = offset % NIR_ALIGN_MUL_MAX;
/xsrc/external/mit/MesaLib/dist/src/microsoft/clc/
H A Dclc_compiler.c644 unsigned align_mul = 0, align_offset = 0; local in function:split_unaligned_loads_stores
645 nir_get_explicit_deref_align(deref, true, &align_mul, &align_offset);
647 unsigned alignment = align_offset ? 1 << (ffs(align_offset) - 1) : align_mul;
H A Dclc_nir.c198 deref->cast.align_offset = nir_intrinsic_align_offset(intr);
/xsrc/external/mit/MesaLib/dist/src/panfrost/lib/
H A Dpan_indirect_dispatch.c54 .align_offset = 0,
/xsrc/external/mit/MesaLib/dist/src/freedreno/ir3/
H A Dir3_nir.c158 ir3_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset, argument
173 align_offset &= 15;
179 unsigned worst_start_offset = 16 - align_mul + align_offset;

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