Searched refs:baseAlign (Results 1 - 25 of 31) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/amd/addrlib/src/r800/
H A Dsiaddrlib.h156 BOOL_32 isLinear, UINT_32 numSlices, UINT_64* pSliceBytes, UINT_32 baseAlign) const;
196 UINT_32 baseAlign, UINT_32 pitchAlign,
227 UINT_32 bpp, UINT_32 numSamples, UINT_32 baseAlign, UINT_32 pitchAlign,
H A Degbaddrlib.h173 UINT_32 bpp, UINT_32 numSamples, UINT_32 baseAlign, UINT_32 pitchAlign,
181 UINT_32 baseAlign, UINT_32 pitchAlign,
293 BOOL_32 isLinear, UINT_32 numSlices, UINT_64* sliceBytes, UINT_32 baseAlign) const;
H A Degbaddrlib.cpp243 &pOut->baseAlign,
286 pOut->baseAlign,
405 &pOut->baseAlign,
434 pOut->baseAlign,
957 pOut->baseAlign =
1221 *pSizeAlign = out.baseAlign;
3195 UINT_32 baseAlign ///< [in] base alignments
3274 pOut->baseAlign = surfOut.baseAlign;
4015 UINT_32 baseAlign local in function:Addr::V1::EgBasedLib::HwlComputeHtileBaseAlign
4089 HwlGetSizeAdjustmentMicroTiled(UINT_32 thickness,UINT_32 bpp,ADDR_SURFACE_FLAGS flags,UINT_32 numSamples,UINT_32 baseAlign,UINT_32 pitchAlign,UINT_32 * pPitch,UINT_32 * pHeight) const argument
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H A Dsiaddrlib.cpp1274 UINT_32 baseAlign ///< [in] base alignments
1277 return ComputeHtileBytes(pitch, height, bpp, isLinear, numSlices, pSliceBytes, baseAlign);
1686 UINT_32 baseAlign, ///< [in] base alignment
1841 UINT_32 baseAlign, ///< [in] base alignment
1861 while ((physicalSliceSize % baseAlign) != 0)
1884 while ((logicalSiceSizeStencil % baseAlign) != 0)
3528 UINT_32 baseAlign = tileSize * pipes * m_tileTable[i].info.banks * local in function:Addr::V1::SiLib::HwlComputeMaxBaseAlignments
3531 if (baseAlign > maxBaseAlign)
3533 maxBaseAlign = baseAlign;
3595 pOut->baseAlign *
1682 HwlGetSizeAdjustmentLinear(AddrTileMode tileMode,UINT_32 bpp,UINT_32 numSamples,UINT_32 baseAlign,UINT_32 pitchAlign,UINT_32 * pPitch,UINT_32 * pHeight,UINT_32 * pHeightAlign) const argument
1836 HwlGetSizeAdjustmentMicroTiled(UINT_32 thickness,UINT_32 bpp,ADDR_SURFACE_FLAGS flags,UINT_32 numSamples,UINT_32 baseAlign,UINT_32 pitchAlign,UINT_32 * pPitch,UINT_32 * pHeight) const argument
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H A Dciaddrlib.cpp2183 UINT_32 baseAlign = tileSize * pipes * m_macroTileTable[i].banks * local in function:Addr::V1::CiLib::HwlComputeMaxBaseAlignments
2186 if (baseAlign > maxBaseAlign)
2188 maxBaseAlign = baseAlign;
/xsrc/external/mit/MesaLib/dist/src/amd/addrlib/src/r800/
H A Dsiaddrlib.h155 BOOL_32 isLinear, UINT_32 numSlices, UINT_64* pSliceBytes, UINT_32 baseAlign) const;
195 UINT_32 baseAlign, UINT_32 pitchAlign,
226 UINT_32 bpp, UINT_32 numSamples, UINT_32 baseAlign, UINT_32 pitchAlign,
H A Degbaddrlib.h173 UINT_32 bpp, UINT_32 numSamples, UINT_32 baseAlign, UINT_32 pitchAlign,
181 UINT_32 baseAlign, UINT_32 pitchAlign,
293 BOOL_32 isLinear, UINT_32 numSlices, UINT_64* sliceBytes, UINT_32 baseAlign) const;
H A Degbaddrlib.cpp240 &pOut->baseAlign,
283 pOut->baseAlign,
402 &pOut->baseAlign,
431 pOut->baseAlign,
955 pOut->baseAlign =
1218 *pSizeAlign = out.baseAlign;
3200 UINT_32 baseAlign ///< [in] base alignments
3279 pOut->baseAlign = surfOut.baseAlign;
4020 UINT_32 baseAlign local in function:Addr::V1::EgBasedLib::HwlComputeHtileBaseAlign
4094 HwlGetSizeAdjustmentMicroTiled(UINT_32 thickness,UINT_32 bpp,ADDR_SURFACE_FLAGS flags,UINT_32 numSamples,UINT_32 baseAlign,UINT_32 pitchAlign,UINT_32 * pPitch,UINT_32 * pHeight) const argument
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H A Dsiaddrlib.cpp1273 UINT_32 baseAlign ///< [in] base alignments
1276 return ComputeHtileBytes(pitch, height, bpp, isLinear, numSlices, pSliceBytes, baseAlign);
1686 UINT_32 baseAlign, ///< [in] base alignment
1841 UINT_32 baseAlign, ///< [in] base alignment
1861 while ((physicalSliceSize % baseAlign) != 0)
1884 while ((logicalSiceSizeStencil % baseAlign) != 0)
3528 UINT_32 baseAlign = tileSize * pipes * m_tileTable[i].info.banks * local in function:Addr::V1::SiLib::HwlComputeMaxBaseAlignments
3531 if (baseAlign > maxBaseAlign)
3533 maxBaseAlign = baseAlign;
3595 pOut->baseAlign *
1682 HwlGetSizeAdjustmentLinear(AddrTileMode tileMode,UINT_32 bpp,UINT_32 numSamples,UINT_32 baseAlign,UINT_32 pitchAlign,UINT_32 * pPitch,UINT_32 * pHeight,UINT_32 * pHeightAlign) const argument
1836 HwlGetSizeAdjustmentMicroTiled(UINT_32 thickness,UINT_32 bpp,ADDR_SURFACE_FLAGS flags,UINT_32 numSamples,UINT_32 baseAlign,UINT_32 pitchAlign,UINT_32 * pPitch,UINT_32 * pHeight) const argument
[all...]
H A Dciaddrlib.cpp2199 UINT_32 baseAlign = tileSize * pipes * m_macroTileTable[i].banks * local in function:Addr::V1::CiLib::HwlComputeMaxBaseAlignments
2202 if (baseAlign > maxBaseAlign)
2204 maxBaseAlign = baseAlign;
/xsrc/external/mit/MesaLib.old/dist/src/amd/addrlib/src/core/
H A Daddrlib1.cpp429 ValidBaseAlignments(pOut->baseAlign);
898 ValidBaseAlignments(pOut->baseAlign);
1310 pOut->baseAlign = align;
1331 &pOut->baseAlign);
1336 ValidMetaBaseAlignments(pOut->baseAlign);
1399 &pOut->baseAlign,
1404 ValidMetaBaseAlignments(pOut->baseAlign);
1845 UINT_32 baseAlign; local in function:Addr::V1::Lib::ComputeHtileInfo
1873 baseAlign = HwlComputeHtileBaseAlign(flags.tcCompatible, isLinear, pTileInfo);
1881 baseAlign);
1915 UINT_32 baseAlign = m_pipeInterleaveBytes * HwlGetPipes(pTileInfo); local in function:Addr::V1::Lib::ComputeCmaskBaseAlign
1981 UINT_32 baseAlign; local in function:Addr::V1::Lib::ComputeCmaskInfo
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H A Daddrlib.cpp403 pOut->baseAlign = m_maxBaseAlign;
443 pOut->baseAlign = m_maxMetaBaseAlign;
H A Daddrlib2.cpp296 ValidBaseAlignments(pOut->baseAlign);
450 ValidMetaBaseAlignments(pOut->baseAlign);
550 ValidMetaBaseAlignments(pOut->baseAlign);
685 pOut->baseAlign = localOut.baseAlign;
694 ValidBaseAlignments(pOut->baseAlign);
1862 ADDR_ASSERT((pOut->surfSize % pOut->baseAlign) == 0);
/xsrc/external/mit/MesaLib.old/dist/src/amd/addrlib/src/core/core/
H A Daddrlib1.cpp429 ValidBaseAlignments(pOut->baseAlign);
898 ValidBaseAlignments(pOut->baseAlign);
1310 pOut->baseAlign = align;
1331 &pOut->baseAlign);
1336 ValidMetaBaseAlignments(pOut->baseAlign);
1399 &pOut->baseAlign,
1404 ValidMetaBaseAlignments(pOut->baseAlign);
1845 UINT_32 baseAlign; local in function:Addr::V1::Lib::ComputeHtileInfo
1873 baseAlign = HwlComputeHtileBaseAlign(flags.tcCompatible, isLinear, pTileInfo);
1881 baseAlign);
1915 UINT_32 baseAlign = m_pipeInterleaveBytes * HwlGetPipes(pTileInfo); local in function:Addr::V1::Lib::ComputeCmaskBaseAlign
1981 UINT_32 baseAlign; local in function:Addr::V1::Lib::ComputeCmaskInfo
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H A Daddrlib.cpp403 pOut->baseAlign = m_maxBaseAlign;
443 pOut->baseAlign = m_maxMetaBaseAlign;
H A Daddrlib2.cpp296 ValidBaseAlignments(pOut->baseAlign);
450 ValidMetaBaseAlignments(pOut->baseAlign);
550 ValidMetaBaseAlignments(pOut->baseAlign);
685 pOut->baseAlign = localOut.baseAlign;
694 ValidBaseAlignments(pOut->baseAlign);
1862 ADDR_ASSERT((pOut->surfSize % pOut->baseAlign) == 0);
/xsrc/external/mit/MesaLib/dist/src/amd/addrlib/src/core/
H A Daddrlib1.cpp431 ValidBaseAlignments(pOut->baseAlign);
900 ValidBaseAlignments(pOut->baseAlign);
1314 pOut->baseAlign = align;
1335 &pOut->baseAlign);
1340 ValidMetaBaseAlignments(pOut->baseAlign);
1403 &pOut->baseAlign,
1408 ValidMetaBaseAlignments(pOut->baseAlign);
1849 UINT_32 baseAlign; local in function:Addr::V1::Lib::ComputeHtileInfo
1877 baseAlign = HwlComputeHtileBaseAlign(flags.tcCompatible, isLinear, pTileInfo);
1885 baseAlign);
1919 UINT_32 baseAlign = m_pipeInterleaveBytes * HwlGetPipes(pTileInfo); local in function:Addr::V1::Lib::ComputeCmaskBaseAlign
1985 UINT_32 baseAlign; local in function:Addr::V1::Lib::ComputeCmaskInfo
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H A Daddrlib.cpp414 pOut->baseAlign = m_maxBaseAlign;
454 pOut->baseAlign = m_maxMetaBaseAlign;
H A Daddrlib2.cpp323 ValidBaseAlignments(pOut->baseAlign);
478 ValidMetaBaseAlignments(pOut->baseAlign);
578 ValidMetaBaseAlignments(pOut->baseAlign);
713 pOut->baseAlign = localOut.baseAlign;
722 ValidBaseAlignments(pOut->baseAlign);
1970 ADDR_ASSERT((pOut->surfSize % pOut->baseAlign) == 0);
/xsrc/external/mit/MesaLib.old/dist/src/amd/addrlib/inc/
H A Daddrinterface.h597 UINT_32 baseAlign; ///< Base address alignment member in struct:_ADDR_COMPUTE_SURFACE_INFO_OUTPUT
903 UINT_32 baseAlign; ///< Base alignment member in struct:_ADDR_COMPUTE_HTILE_INFO_OUTPUT
1116 UINT_32 baseAlign; ///< Base alignment member in struct:_ADDR_COMPUTE_CMASK_INFO_OUTPUT
1307 UINT_32 baseAlign; ///< Base address alignment member in struct:_ADDR_COMPUTE_FMASK_INFO_OUTPUT
2280 UINT_32 baseAlign; ///< Maximum base alignment in bytes member in struct:_ADDR_GET_MAX_ALINGMENTS_OUTPUT
2453 UINT_32 baseAlign; ///< Base address alignment member in struct:_ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
2724 UINT_32 baseAlign; ///< Base alignment member in struct:_ADDR2_COMPUTE_HTILE_INFO_OUTPUT
2904 UINT_32 baseAlign; ///< Base alignment member in struct:_ADDR2_COMPUTE_CMASK_INFO_OUTPUT
3107 UINT_32 baseAlign; ///< Base alignment member in struct:_ADDR2_COMPUTE_FMASK_INFO_OUTPUT
/xsrc/external/mit/MesaLib.old/dist/src/amd/addrlib/src/gfx9/
H A Dgfx9addrlib.h380 UINT_32 baseAlign; local in function:Addr::V2::Gfx9Lib::ComputeSurfaceBaseAlignTiled
384 baseAlign = GetBlockSize(swizzleMode);
388 baseAlign = 256;
391 return baseAlign;
/xsrc/external/mit/MesaLib/dist/src/amd/addrlib/src/gfx9/
H A Dgfx9addrlib.h518 UINT_32 baseAlign; local in function:Addr::V2::Gfx9Lib::ComputeSurfaceBaseAlignTiled
522 baseAlign = GetBlockSize(swizzleMode);
526 baseAlign = 256;
529 return baseAlign;
/xsrc/external/mit/MesaLib.old/dist/src/amd/common/
H A Dac_surface.c232 *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
347 surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
439 surf->htile_alignment = AddrHtileOut->baseAlign;
512 surf->surf_alignment = csio->baseAlign;
949 surf->fmask_alignment = fout.baseAlign;
1102 surf->surf_alignment = MAX2(surf->surf_alignment, out.baseAlign);
1103 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign);
1122 surf->surf_alignment = out.baseAlign;
1157 surf->htile_alignment = hout.baseAlign;
1385 surf->fmask_alignment = fout.baseAlign;
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/xsrc/external/mit/MesaLib/dist/src/amd/addrlib/inc/
H A Daddrinterface.h600 UINT_32 baseAlign; ///< Base address alignment member in struct:_ADDR_COMPUTE_SURFACE_INFO_OUTPUT
910 UINT_32 baseAlign; ///< Base alignment member in struct:_ADDR_COMPUTE_HTILE_INFO_OUTPUT
1129 UINT_32 baseAlign; ///< Base alignment member in struct:_ADDR_COMPUTE_CMASK_INFO_OUTPUT
1326 UINT_32 baseAlign; ///< Base address alignment member in struct:_ADDR_COMPUTE_FMASK_INFO_OUTPUT
2327 UINT_32 baseAlign; ///< Maximum base alignment in bytes member in struct:ADDR_GET_MAX_ALINGMENTS_OUTPUT
2501 UINT_32 baseAlign; ///< Base address alignment member in struct:_ADDR2_COMPUTE_SURFACE_INFO_OUTPUT
2780 UINT_32 baseAlign; ///< Base alignment member in struct:_ADDR2_COMPUTE_HTILE_INFO_OUTPUT
2988 UINT_32 baseAlign; ///< Base alignment member in struct:_ADDR2_COMPUTE_CMASK_INFO_OUTPUT
3214 UINT_32 baseAlign; ///< Base alignment member in struct:_ADDR2_COMPUTE_FMASK_INFO_OUTPUT
/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_surface.c495 *max_alignment = addrGetMaxAlignmentsOutput.baseAlign;
635 surf_level->offset_256B = align64(surf->surf_size, AddrSurfInfoOut->baseAlign) / 256;
773 surf->meta_alignment_log2 = util_logbase2(AddrHtileOut->baseAlign);
846 surf->surf_alignment_log2 = util_logbase2(csio->baseAlign);
1265 surf->fmask_alignment_log2 = util_logbase2(fout.baseAlign);
1666 surf->surf_alignment_log2 = MAX2(surf->surf_alignment_log2, util_logbase2(out.baseAlign));
1667 surf->u.gfx9.zs.stencil_offset = align(surf->surf_size, out.baseAlign);
1687 surf->surf_alignment_log2 = util_logbase2(out.baseAlign);
1750 surf->meta_alignment_log2 = util_logbase2(hout.baseAlign);
1953 surf->fmask_alignment_log2 = util_logbase2(fout.baseAlign);
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