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    Searched refs:base_reg (Results 1 - 12 of 12) sorted by relevancy

  /xsrc/external/mit/MesaLib/dist/src/util/
register_allocate.h 62 unsigned int base_reg, unsigned int reg);
66 unsigned int base_reg, unsigned int reg0, unsigned int reg1);
register_allocate.c 152 * Adds a conflict between base_reg and reg, and also between reg and
153 * anything that base_reg conflicts with.
161 unsigned int base_reg, unsigned int reg)
163 ra_add_reg_conflict(regs, reg, base_reg);
165 util_dynarray_foreach(&regs->regs[base_reg].conflict_list, unsigned int,
172 * Set up conflicts between base_reg and it's two half registers reg0 and
180 unsigned int base_reg, unsigned int reg0, unsigned int reg1)
182 ra_add_reg_conflict(regs, reg0, base_reg);
183 ra_add_reg_conflict(regs, reg1, base_reg);
185 util_dynarray_foreach(&regs->regs[base_reg].conflict_list, unsigned int, i)
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/util/
register_allocate.h 57 unsigned int base_reg, unsigned int reg);
register_allocate.c 260 * Adds a conflict between base_reg and reg, and also between reg and
261 * anything that base_reg conflicts with.
269 unsigned int base_reg, unsigned int reg)
273 ra_add_reg_conflict(regs, reg, base_reg);
275 for (i = 0; i < regs->regs[base_reg].num_conflicts; i++) {
276 ra_add_reg_conflict(regs, reg, regs->regs[base_reg].conflict_list[i]);
  /xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
brw_vec4_reg_allocate.cpp 138 for (int base_reg = j;
139 base_reg < j + class_sizes[i];
140 base_reg++) {
141 ra_add_reg_conflict(compiler->vec4_reg_set.regs, base_reg, reg);
brw_fs_reg_allocate.cpp 217 for (int base_reg = j;
218 base_reg < j + (class_sizes[i] + 1) / 2;
219 base_reg++) {
220 ra_add_reg_conflict(regs, base_reg, reg);
231 for (int base_reg = j;
232 base_reg < j + class_sizes[i];
233 base_reg++) {
234 ra_add_reg_conflict(regs, base_reg, reg);
  /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/radeon/
radeon_state_init.c 426 uint32_t base_reg; local
439 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break;
440 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break;
442 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break;
448 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0));
  /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
radv_cmd_buffer.c 592 uint32_t base_reg = pipeline->user_data_0[stage]; local
599 base_reg + loc->sgpr_idx * 4, va, false);
642 uint32_t base_reg = pipeline->user_data_0[stage]; local
648 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
2052 uint32_t base_reg; local
2063 base_reg = pipeline->user_data_0[stage];
2066 base_reg + loc->sgpr_idx * 4, va, false);
2072 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0;
2075 base_reg + loc->sgpr_idx * 4, va, false);
3563 uint32_t base_reg = pipeline->user_data_0[stage] local
3570 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0; local
3611 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr; local
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/radeon/
radeon_state_init.c 427 uint32_t base_reg; local
440 case 1: base_reg = RADEON_PP_CUBIC_OFFSET_T1_0; break;
441 case 2: base_reg = RADEON_PP_CUBIC_OFFSET_T2_0; break;
443 case 0: base_reg = RADEON_PP_CUBIC_OFFSET_T0_0; break;
449 OUT_BATCH(CP_PACKET0(base_reg + (4 * j), 0));
  /xsrc/external/mit/MesaLib/dist/src/freedreno/ir3/
ir3_spill.c 125 struct ir3_register *base_reg; member in struct:ra_spill_ctx
161 ctx->base_reg = mov->dsts[0];
167 ctx->limit_pressure.full -= reg_size(ctx->base_reg);
676 ir3_src_create(spill, INVALID_REG, ctx->base_reg->flags)->def = ctx->base_reg;
835 ir3_src_create(reload, INVALID_REG, ctx->base_reg->flags)->def = ctx->base_reg;
1743 instr->dsts[0] == ctx->base_reg)
  /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
radv_cmd_buffer.c 792 uint32_t base_reg = pipeline->user_data_0[stage]; local
798 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, va,
1014 uint32_t base_reg = pipeline->user_data_0[stage]; local
1020 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, loc->num_sgprs);
2963 uint32_t base_reg = cmd_buffer->state.pipeline->user_data_0[MESA_SHADER_VERTEX]; local
2966 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,
3469 uint32_t base_reg; local
3479 base_reg = pipeline->user_data_0[stage];
3481 radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, va,
3488 base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0
3568 uint32_t base_reg; local
5929 uint32_t base_reg = pipeline->user_data_0[stage]; local
5936 uint32_t base_reg = R_00B130_SPI_SHADER_USER_DATA_VS_0; local
5982 uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr; local
6457 const uint32_t base_reg = pipeline->user_data_0[stage]; local
7181 uint32_t base_reg; local
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/freedreno/decode/
cffdec.c 1457 const unsigned base_reg = stage == MESA_SHADER_COMPUTE local
1462 const unsigned reg = base_reg + (dwords[1] >> 28) * 2;
1466 const unsigned reg = base_reg + (dwords[1] >> 28);

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