Searched refs:dcc (Results 1 - 25 of 30) sorted by relevance

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/xsrc/external/mit/xcmsdb/dist/
H A DMakefile.am33 EXTRA_DIST = datafiles/sample1.dcc datafiles/sample2.dcc README.md
H A DMakefile.in385 EXTRA_DIST = datafiles/sample1.dcc datafiles/sample2.dcc README.md
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/sb/
H A Dsb_peephole.cpp249 unsigned dcc = dflags & AF_CC_MASK; local in function:r600_sb::peephole::optimize_CNDcc_op
275 if (dcc == AF_CC_NE) {
276 dcc = AF_CC_E;
281 switch (dcc) {
282 case AF_CC_GT: dcc = AF_CC_GE; swap = !swap; break;
283 case AF_CC_GE: dcc = AF_CC_GT; swap = !swap; break;
296 a->bc.set_op(get_cndcc_op(dcc, dcmp_type));
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/sb/
H A Dsb_peephole.cpp249 unsigned dcc = dflags & AF_CC_MASK; local in function:r600_sb::peephole::optimize_CNDcc_op
275 if (dcc == AF_CC_NE) {
276 dcc = AF_CC_E;
281 switch (dcc) {
282 case AF_CC_GT: dcc = AF_CC_GE; swap = !swap; break;
283 case AF_CC_GE: dcc = AF_CC_GT; swap = !swap; break;
296 a->bc.set_op(get_cndcc_op(dcc, dcmp_type));
/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_surface.c150 return (!surf->u.gfx9.color.dcc.independent_64B_blocks &&
151 surf->u.gfx9.color.dcc.independent_128B_blocks &&
152 surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_128B) ||
154 surf->u.gfx9.color.dcc.independent_64B_blocks &&
155 surf->u.gfx9.color.dcc.independent_128B_blocks &&
156 surf->u.gfx9.color.dcc.max_compressed_block_size == V_028C78_MAX_BLOCK_SIZE_64B);
185 surf->u.gfx9.color.dcc.independent_64B_blocks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier);
186 surf->u.gfx9.color.dcc.independent_128B_blocks = AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier);
187 surf->u.gfx9.color.dcc.max_compressed_block_size = AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier);
235 if (!options->dcc)
1554 ac_copy_dcc_equation(const struct radeon_info * info,ADDR2_COMPUTE_DCCINFO_OUTPUT * dcc,struct gfx9_meta_equation * equation) argument
[all...]
H A Dac_surface_modifier_test.c86 din.dccKeyFlags.pipeAligned = surf->u.gfx9.color.dcc.pipe_aligned;
87 din.dccKeyFlags.rbAligned = surf->u.gfx9.color.dcc.rb_aligned;
148 surf->u.gfx9.color.dcc.rb_aligned,
149 surf->u.gfx9.color.dcc.pipe_aligned);
345 .dcc = true,
H A Dac_surface.h179 * ac_nir_{dcc,htile}_addr_from_coord is the NIR implementation.
260 struct gfx9_surf_meta_flags dcc; /* metadata of color */ member in struct:gfx9_surf_layout::__anon37701e37080a::__anon37701e370908
442 bool dcc; /* Whether to allow DCC. */ member in struct:ac_modifier_options
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_sdma_copy_image.c164 bool dcc = vi_dcc_enabled(tiled, 0) && is_v5; local in function:si_sdma_v4_v5_copy_texture
180 dcc << 19 |
200 if (dcc) {
212 tiled->surface.u.gfx9.color.dcc.max_compressed_block_size << 24 |
215 tiled->surface.u.gfx9.color.dcc.pipe_aligned << 31);
H A Dsi_compute_blit.c481 ssrc->surface.u.gfx9.color.dcc.pipe_aligned);
485 sdst->surface.u.gfx9.color.dcc.pipe_aligned);
709 ((struct si_texture*)tex)->surface.u.gfx9.color.dcc.pipe_aligned);
802 tex->surface.u.gfx9.color.dcc.pipe_aligned);
H A Dsi_state.c2479 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(tex->surface.u.gfx9.color.dcc.max_compressed_block_size) |
2481 S_028C78_INDEPENDENT_64B_BLOCKS(tex->surface.u.gfx9.color.dcc.independent_64B_blocks) |
2482 S_028C78_INDEPENDENT_128B_BLOCKS(tex->surface.u.gfx9.color.dcc.independent_128B_blocks);
2915 if (sctx->chip_class >= GFX9 && !tex->surface.u.gfx9.color.dcc.pipe_aligned)
3136 S_028EE0_DCC_PIPE_ALIGNED(tex->surface.u.gfx9.color.dcc.pipe_aligned);
3169 meta = tex->surface.u.gfx9.color.dcc;
3896 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(tex->surface.u.gfx9.color.dcc.max_compressed_block_size) |
H A Dsi_blit.c529 tex->surface.u.gfx9.color.dcc.pipe_aligned);
H A Dsi_descriptors.c359 meta = tex->surface.u.gfx9.color.dcc;
405 meta = tex->surface.u.gfx9.color.dcc;
H A Dsi_texture.c1322 .dcc = !(sscreen->debug_flags & DBG(NO_DCC)),
/xsrc/external/mit/MesaLib.old/dist/src/amd/common/
H A Dac_surface.h142 struct gfx9_surf_meta_flags dcc; /* metadata of color */ member in struct:gfx9_surf_layout
H A Dac_surface.c1220 surf->u.gfx9.dcc.rb_aligned = din.dccKeyFlags.rbAligned;
1221 surf->u.gfx9.dcc.pipe_aligned = din.dccKeyFlags.pipeAligned;
1274 assert(surf->u.gfx9.dcc.pipe_aligned ||
1275 surf->u.gfx9.dcc.rb_aligned);
1324 addrin.dccKeyFlags.pipeAligned = surf->u.gfx9.dcc.pipe_aligned;
1325 addrin.dccKeyFlags.rbAligned = surf->u.gfx9.dcc.rb_aligned;
1649 (surf->u.gfx9.dcc.pipe_aligned ||
1650 surf->u.gfx9.dcc.rb_aligned))
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D21.3.4.rst140 - radeonsi/gfx8: use the proper dcc clear size
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_image.c788 meta = plane->surface.u.gfx9.color.dcc;
819 meta = plane->surface.u.gfx9.color.dcc;
964 image->planes[0].surface.u.gfx9.color.dcc.max_compressed_block_size) |
1274 metadata->u.gfx9.dcc_independent_64b_blocks = surface->u.gfx9.color.dcc.independent_64B_blocks;
1275 metadata->u.gfx9.dcc_independent_128b_blocks = surface->u.gfx9.color.dcc.independent_128B_blocks;
1277 surface->u.gfx9.color.dcc.max_compressed_block_size;
1668 .dcc = true,
H A Dradv_formats.c1187 .dcc = true,
H A Dradv_device.c6561 iview->image->planes[0].surface.u.gfx9.color.dcc.max_compressed_block_size;
6562 independent_128b_blocks = iview->image->planes[0].surface.u.gfx9.color.dcc.independent_128B_blocks;
6563 independent_64b_blocks = iview->image->planes[0].surface.u.gfx9.color.dcc.independent_64B_blocks;
6618 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.color.dcc.pipe_aligned);
6626 meta = surf->u.gfx9.color.dcc;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_compute_blit.c341 ((struct si_texture*)src)->surface.u.gfx9.dcc.pipe_aligned);
H A Dsi_texture.c737 tex->surface.u.gfx9.dcc.pipe_aligned =
739 tex->surface.u.gfx9.dcc.rb_aligned =
743 if (!tex->surface.u.gfx9.dcc.pipe_aligned &&
744 !tex->surface.u.gfx9.dcc.rb_aligned)
768 !tex->surface.u.gfx9.dcc.pipe_aligned &&
769 !tex->surface.u.gfx9.dcc.rb_aligned)
H A Dsi_blit.c538 tex->surface.u.gfx9.dcc.pipe_aligned);
H A Dsi_descriptors.c393 meta = tex->surface.u.gfx9.dcc;
H A Dsi_state.c2922 !tex->surface.u.gfx9.dcc.pipe_aligned)
3106 meta = tex->surface.u.gfx9.dcc;
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_image.c411 meta = plane->surface.u.gfx9.dcc;
885 /* + 16 for storing the clear values + dcc pred */

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