Searched refs:dispatch_width (Results 1 - 25 of 34) sorted by relevance

12

/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen8_eu.h6 bool gen8_wm_kernel__affine(struct brw_compile *p, int dispatch_width);
7 bool gen8_wm_kernel__affine_mask(struct brw_compile *p, int dispatch_width);
8 bool gen8_wm_kernel__affine_mask_ca(struct brw_compile *p, int dispatch_width);
9 bool gen8_wm_kernel__affine_mask_sa(struct brw_compile *p, int dispatch_width);
11 bool gen8_wm_kernel__projective(struct brw_compile *p, int dispatch_width);
12 bool gen8_wm_kernel__projective_mask(struct brw_compile *p, int dispatch_width);
13 bool gen8_wm_kernel__projective_mask_ca(struct brw_compile *p, int dispatch_width);
14 bool gen8_wm_kernel__projective_mask_sa(struct brw_compile *p, int dispatch_width);
16 bool gen8_wm_kernel__affine_opacity(struct brw_compile *p, int dispatch_width);
17 bool gen8_wm_kernel__projective_opacity(struct brw_compile *p, int dispatch_width);
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H A Dsna_stream.c127 int dispatch_width)
135 if (!compile(&p, dispatch_width)) {
124 sna_static_stream_compile_wm(struct sna * sna,struct sna_static_stream * stream,bool (* compile)(struct brw_compile *,int),int dispatch_width) argument
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen8_eu.h6 bool gen8_wm_kernel__affine(struct brw_compile *p, int dispatch_width);
7 bool gen8_wm_kernel__affine_mask(struct brw_compile *p, int dispatch_width);
8 bool gen8_wm_kernel__affine_mask_ca(struct brw_compile *p, int dispatch_width);
9 bool gen8_wm_kernel__affine_mask_sa(struct brw_compile *p, int dispatch_width);
11 bool gen8_wm_kernel__projective(struct brw_compile *p, int dispatch_width);
12 bool gen8_wm_kernel__projective_mask(struct brw_compile *p, int dispatch_width);
13 bool gen8_wm_kernel__projective_mask_ca(struct brw_compile *p, int dispatch_width);
14 bool gen8_wm_kernel__projective_mask_sa(struct brw_compile *p, int dispatch_width);
16 bool gen8_wm_kernel__affine_opacity(struct brw_compile *p, int dispatch_width);
17 bool gen8_wm_kernel__projective_opacity(struct brw_compile *p, int dispatch_width);
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H A Dsna_stream.c127 int dispatch_width)
135 if (!compile(&p, dispatch_width)) {
124 sna_static_stream_compile_wm(struct sna * sna,struct sna_static_stream * stream,bool (* compile)(struct brw_compile *,int),int dispatch_width) argument
/xsrc/external/mit/xf86-video-intel/dist/src/sna/brw/
H A Dbrw.h6 bool brw_wm_kernel__affine(struct brw_compile *p, int dispatch_width);
7 bool brw_wm_kernel__affine_mask(struct brw_compile *p, int dispatch_width);
8 bool brw_wm_kernel__affine_mask_ca(struct brw_compile *p, int dispatch_width);
9 bool brw_wm_kernel__affine_mask_sa(struct brw_compile *p, int dispatch_width);
11 bool brw_wm_kernel__projective(struct brw_compile *p, int dispatch_width);
12 bool brw_wm_kernel__projective_mask(struct brw_compile *p, int dispatch_width);
13 bool brw_wm_kernel__projective_mask_ca(struct brw_compile *p, int dispatch_width);
14 bool brw_wm_kernel__projective_mask_sa(struct brw_compile *p, int dispatch_width);
16 bool brw_wm_kernel__affine_opacity(struct brw_compile *p, int dispatch_width);
17 bool brw_wm_kernel__projective_opacity(struct brw_compile *p, int dispatch_width);
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/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/brw/
H A Dbrw.h6 bool brw_wm_kernel__affine(struct brw_compile *p, int dispatch_width);
7 bool brw_wm_kernel__affine_mask(struct brw_compile *p, int dispatch_width);
8 bool brw_wm_kernel__affine_mask_ca(struct brw_compile *p, int dispatch_width);
9 bool brw_wm_kernel__affine_mask_sa(struct brw_compile *p, int dispatch_width);
11 bool brw_wm_kernel__projective(struct brw_compile *p, int dispatch_width);
12 bool brw_wm_kernel__projective_mask(struct brw_compile *p, int dispatch_width);
13 bool brw_wm_kernel__projective_mask_ca(struct brw_compile *p, int dispatch_width);
14 bool brw_wm_kernel__projective_mask_sa(struct brw_compile *p, int dispatch_width);
16 bool brw_wm_kernel__affine_opacity(struct brw_compile *p, int dispatch_width);
17 bool brw_wm_kernel__projective_opacity(struct brw_compile *p, int dispatch_width);
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/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dbrw_fs_builder.h53 * \p dispatch_width gives the native execution width of the program.
56 unsigned dispatch_width) :
58 _dispatch_width(dispatch_width),
119 if (n <= dispatch_width() && i < dispatch_width() / n) {
178 dispatch_width() const function in class:brw::fs_builder
195 * dispatch_width units (which is just enough space for one logical
201 assert(dispatch_width() <= 32);
205 DIV_ROUND_UP(n * type_sz(type) * dispatch_width(),
257 assert(shader->devinfo->gen >= 6 && dispatch_width() <
55 fs_builder(backend_shader * shader,unsigned dispatch_width) argument
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H A Dbrw_nir_lower_cs_intrinsics.c29 unsigned dispatch_width; member in struct:lower_intrinsics_state
65 if (state->local_workgroup_size <= state->dispatch_width)
71 nir_imul_imm(b, subgroup_id, state->dispatch_width);
159 DIV_ROUND_UP(local_workgroup_size, state->dispatch_width);
192 unsigned dispatch_width)
198 .dispatch_width = dispatch_width,
191 brw_nir_lower_cs_intrinsics(nir_shader * nir,unsigned dispatch_width) argument
H A Dbrw_vec4_builder.h54 vec4_builder(backend_shader *shader, unsigned dispatch_width = 8) : argument
56 _dispatch_width(dispatch_width), _group(0),
114 (n <= dispatch_width() && i < dispatch_width() / n));
151 dispatch_width() const function in class:brw::vec4_builder
168 * dispatch_width units (which is just enough space for four logical
174 assert(dispatch_width() <= 32);
190 return dst_reg(retype(brw_null_vec(dispatch_width()),
200 return dst_reg(retype(brw_null_vec(dispatch_width()),
210 return dst_reg(retype(brw_null_vec(dispatch_width()),
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H A Dbrw_fs_visitor.cpp96 int reg_width = dispatch_width / 8;
179 if (devinfo->has_pln && dispatch_width == 16) {
212 for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) {
213 const fs_builder hbld = abld.group(MIN2(16, dispatch_width), i);
216 if (devinfo->gen >= 8 || dispatch_width == 8) {
228 abld.exec_all().group(hbld.dispatch_width() * 2, 0);
286 for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) {
298 for (unsigned q = 0; q < dispatch_width / 8; q++) {
300 const unsigned idx = c + (q & 2) + (q & 1) * dispatch_width / 8;
976 unsigned dispatch_width,
970 fs_visitor(const struct brw_compiler * compiler,void * log_data,void * mem_ctx,const void * key,struct brw_stage_prog_data * prog_data,struct gl_program * prog,const nir_shader * shader,unsigned dispatch_width,int shader_time_index,const struct brw_vue_map * input_vue_map) argument
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H A Dbrw_fs_reg_allocate.cpp49 int reg_width = dispatch_width / 8;
76 brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width) argument
80 const int index = _mesa_logbase2(dispatch_width / 8);
82 if (dispatch_width > 8 && devinfo->gen >= 7) {
118 if (devinfo->gen <= 5 && dispatch_width >= 16) {
165 if (devinfo->gen <= 5 && dispatch_width >= 16) {
211 if (devinfo->gen <= 5 && dispatch_width >= 16) {
252 if (devinfo->has_pln && dispatch_width == 8 && devinfo->gen <= 6) {
447 if (devinfo->gen <= 5 && dispatch_width >= 16) {
471 int reg_width = v->dispatch_width /
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H A Dbrw_fs.h50 return offset(reg, bld.dispatch_width(), delta);
69 unsigned dispatch_width,
387 const unsigned dispatch_width; /**< 8, 16 or 32 */ member in class:fs_visitor
422 int generate_code(const cfg_t *cfg, int dispatch_width);
517 unsigned dispatch_width; /**< 8, 16 or 32 */ member in class:fs_generator
536 if (bld.dispatch_width() > 16) {
539 const unsigned m = bld.dispatch_width() / hbld.dispatch_width();
H A Dbrw_nir.h104 unsigned dispatch_width);
H A Dbrw_wm_iz.cpp125 assert(dispatch_width <= 16);
H A Dbrw_fs.cpp666 if (dispatch_width == 8)
718 if (dispatch_width > n) {
1104 return 1 * dispatch_width / 8;
1108 return 2 * dispatch_width / 8;
1140 int reg_width = dispatch_width / 8;
1389 for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) {
1390 const fs_builder hbld = abld.group(MIN2(16, dispatch_width), i);
2818 if (stage != MESA_SHADER_FRAGMENT || dispatch_width > 16)
3435 if (dispatch_width >= 16)
3883 for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width,
8197 compile_cs_to_nir(const struct brw_compiler * compiler,void * mem_ctx,const struct brw_cs_prog_key * key,const nir_shader * src_shader,unsigned dispatch_width) argument
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H A Dbrw_fs_nir.cpp196 for (unsigned i = 0; i < DIV_ROUND_UP(v->dispatch_width, 16); i++) {
197 const fs_builder hbld = abld.group(MIN2(16, v->dispatch_width), i);
257 if (dispatch_width > 8)
259 if (dispatch_width > 16) {
3770 inst->size_written = instr->num_components * dispatch_width * 4;
4022 inst->size_written = instr->num_components * dispatch_width * 4;
4150 inst->size_written = instr->num_components * dispatch_width * 4;
4471 inst->size_written = instr->num_components * dispatch_width * 4;
4662 if (dispatch_width == 32) {
4679 set_predicate(dispatch_width
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/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_fs_builder.h53 * \p dispatch_width gives the native execution width of the program.
56 unsigned dispatch_width) :
58 _dispatch_width(dispatch_width),
119 if (n <= dispatch_width() && i < dispatch_width() / n) {
178 dispatch_width() const function in class:brw::fs_builder
195 * dispatch_width units (which is just enough space for one logical
201 assert(dispatch_width() <= 32);
205 DIV_ROUND_UP(n * type_sz(type) * dispatch_width(),
260 return emit(instruction(opcode, dispatch_width()));
55 fs_builder(backend_shader * shader,unsigned dispatch_width) argument
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H A Dbrw_vec4_builder.h54 vec4_builder(backend_shader *shader, unsigned dispatch_width = 8) : argument
56 _dispatch_width(dispatch_width), _group(0),
114 (n <= dispatch_width() && i < dispatch_width() / n));
151 dispatch_width() const function in class:brw::vec4_builder
168 * dispatch_width units (which is just enough space for four logical
174 assert(dispatch_width() <= 32);
190 return dst_reg(retype(brw_null_vec(dispatch_width()),
200 return dst_reg(retype(brw_null_vec(dispatch_width()),
210 return dst_reg(retype(brw_null_vec(dispatch_width()),
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H A Dbrw_fs_visitor.cpp96 int reg_width = dispatch_width / 8;
181 for (unsigned i = 0; i < dispatch_width / 8; i++) {
345 abld.exec_all().group(MIN2(16, dispatch_width) * 2, 0);
381 for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) {
382 const fs_builder hbld = abld.group(MIN2(16, dispatch_width), i);
387 abld.exec_all().group(hbld.dispatch_width() * 2, 0);
408 } else if (devinfo->ver >= 8 || dispatch_width == 8) {
420 abld.exec_all().group(hbld.dispatch_width() * 2, 0);
529 for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) {
545 for (unsigned q = 0; q < dispatch_width /
1091 fs_visitor(const struct brw_compiler * compiler,void * log_data,void * mem_ctx,const brw_base_prog_key * key,struct brw_stage_prog_data * prog_data,const nir_shader * shader,unsigned dispatch_width,int shader_time_index,bool debug_enabled) argument
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H A Dbrw_fs.h78 return offset(reg, bld.dispatch_width(), delta);
99 unsigned dispatch_width,
423 const unsigned dispatch_width; /**< 8, 16 or 32 */ member in class:fs_visitor
476 int generate_code(const cfg_t *cfg, int dispatch_width,
577 unsigned dispatch_width; /**< 8, 16 or 32 */ member in class:fs_generator
595 if (bld.dispatch_width() > 16) {
598 const unsigned m = bld.dispatch_width() / hbld.dispatch_width();
622 const unsigned m = bld.dispatch_width() / hbld.dispatch_width();
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H A Dbrw_fs_reg_allocate.cpp50 int reg_width = dispatch_width / 8;
80 aligned_bary_size(unsigned dispatch_width) argument
82 return (dispatch_width == 8 ? 2 : 4);
86 brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width) argument
90 const int index = util_logbase2(dispatch_width / 8);
92 if (dispatch_width > 8 && devinfo->ver >= 7) {
133 if (devinfo->ver <= 5 && dispatch_width >= 16) {
156 (dispatch_width == 8 && devinfo->ver <= 5))) {
157 int contig_len = aligned_bary_size(dispatch_width);
310 * (dispatch_width
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H A Dbrw_wm_iz.cpp125 assert(dispatch_width <= 16);
H A Dbrw_compiler.h1067 unsigned dispatch_width)
1069 assert(dispatch_width == 8 ||
1070 dispatch_width == 16 ||
1071 dispatch_width == 32);
1072 const unsigned index = dispatch_width / 16;
1468 uint32_t dispatch_width; /**< 0 for vec4 */ member in struct:brw_compile_stats
1066 brw_cs_prog_data_prog_offset(const struct brw_cs_prog_data * prog_data,unsigned dispatch_width) argument
H A Dbrw_fs_nir.cpp46 last_scratch = ALIGN(nir->scratch_size, 4) * dispatch_width;
222 for (unsigned i = 0; i < DIV_ROUND_UP(v->dispatch_width, 16); i++) {
223 const fs_builder hbld = abld.group(MIN2(16, v->dispatch_width), i);
289 if (dispatch_width > 8)
291 if (dispatch_width > 16) {
3818 workgroup_size() <= dispatch_width) {
3863 inst->size_written = 3 * dispatch_width * 4;
3909 inst->size_written = instr->num_components * dispatch_width * 4;
4169 const unsigned chan_index_bits = ffs(dispatch_width) - 1;
4312 inst->size_written = instr->num_components * dispatch_width *
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H A Dbrw_fs.cpp661 if (dispatch_width == 8)
681 dispatch_width, stage_abbrev, msg);
714 if (dispatch_width > n) {
1199 int reg_width = dispatch_width / 8;
1456 for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) {
1457 const fs_builder hbld = abld.group(MIN2(16, dispatch_width), i);
3559 if (dispatch_width >= 16)
4078 fs_reg imm(VGRF, alloc.allocate(dispatch_width / 8), inst->dst.type);
4512 * thread payload, \p bld is required to have a dispatch_width() not greater
4523 assert(bld.dispatch_width() <
10069 brw_nir_lower_simd(nir_shader * nir,unsigned dispatch_width) argument
10076 compile_cs_to_nir(const struct brw_compiler * compiler,void * mem_ctx,const struct brw_cs_prog_key * key,const nir_shader * src_shader,unsigned dispatch_width,bool debug_enabled) argument
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