HomeSort by: relevance | last modified time | path
    Searched refs:dispatch_width (Results 1 - 25 of 34) sorted by relevancy

1 2

  /xsrc/external/mit/xf86-video-intel/dist/src/sna/
gen8_eu.h 6 bool gen8_wm_kernel__affine(struct brw_compile *p, int dispatch_width);
7 bool gen8_wm_kernel__affine_mask(struct brw_compile *p, int dispatch_width);
8 bool gen8_wm_kernel__affine_mask_ca(struct brw_compile *p, int dispatch_width);
9 bool gen8_wm_kernel__affine_mask_sa(struct brw_compile *p, int dispatch_width);
11 bool gen8_wm_kernel__projective(struct brw_compile *p, int dispatch_width);
12 bool gen8_wm_kernel__projective_mask(struct brw_compile *p, int dispatch_width);
13 bool gen8_wm_kernel__projective_mask_ca(struct brw_compile *p, int dispatch_width);
14 bool gen8_wm_kernel__projective_mask_sa(struct brw_compile *p, int dispatch_width);
16 bool gen8_wm_kernel__affine_opacity(struct brw_compile *p, int dispatch_width);
17 bool gen8_wm_kernel__projective_opacity(struct brw_compile *p, int dispatch_width);
    [all...]
sna_stream.c 127 int dispatch_width)
135 if (!compile(&p, dispatch_width)) {
  /xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
gen8_eu.h 6 bool gen8_wm_kernel__affine(struct brw_compile *p, int dispatch_width);
7 bool gen8_wm_kernel__affine_mask(struct brw_compile *p, int dispatch_width);
8 bool gen8_wm_kernel__affine_mask_ca(struct brw_compile *p, int dispatch_width);
9 bool gen8_wm_kernel__affine_mask_sa(struct brw_compile *p, int dispatch_width);
11 bool gen8_wm_kernel__projective(struct brw_compile *p, int dispatch_width);
12 bool gen8_wm_kernel__projective_mask(struct brw_compile *p, int dispatch_width);
13 bool gen8_wm_kernel__projective_mask_ca(struct brw_compile *p, int dispatch_width);
14 bool gen8_wm_kernel__projective_mask_sa(struct brw_compile *p, int dispatch_width);
16 bool gen8_wm_kernel__affine_opacity(struct brw_compile *p, int dispatch_width);
17 bool gen8_wm_kernel__projective_opacity(struct brw_compile *p, int dispatch_width);
    [all...]
sna_stream.c 127 int dispatch_width)
135 if (!compile(&p, dispatch_width)) {
  /xsrc/external/mit/xf86-video-intel/dist/src/sna/brw/
brw.h 6 bool brw_wm_kernel__affine(struct brw_compile *p, int dispatch_width);
7 bool brw_wm_kernel__affine_mask(struct brw_compile *p, int dispatch_width);
8 bool brw_wm_kernel__affine_mask_ca(struct brw_compile *p, int dispatch_width);
9 bool brw_wm_kernel__affine_mask_sa(struct brw_compile *p, int dispatch_width);
11 bool brw_wm_kernel__projective(struct brw_compile *p, int dispatch_width);
12 bool brw_wm_kernel__projective_mask(struct brw_compile *p, int dispatch_width);
13 bool brw_wm_kernel__projective_mask_ca(struct brw_compile *p, int dispatch_width);
14 bool brw_wm_kernel__projective_mask_sa(struct brw_compile *p, int dispatch_width);
16 bool brw_wm_kernel__affine_opacity(struct brw_compile *p, int dispatch_width);
17 bool brw_wm_kernel__projective_opacity(struct brw_compile *p, int dispatch_width);
    [all...]
  /xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/brw/
brw.h 6 bool brw_wm_kernel__affine(struct brw_compile *p, int dispatch_width);
7 bool brw_wm_kernel__affine_mask(struct brw_compile *p, int dispatch_width);
8 bool brw_wm_kernel__affine_mask_ca(struct brw_compile *p, int dispatch_width);
9 bool brw_wm_kernel__affine_mask_sa(struct brw_compile *p, int dispatch_width);
11 bool brw_wm_kernel__projective(struct brw_compile *p, int dispatch_width);
12 bool brw_wm_kernel__projective_mask(struct brw_compile *p, int dispatch_width);
13 bool brw_wm_kernel__projective_mask_ca(struct brw_compile *p, int dispatch_width);
14 bool brw_wm_kernel__projective_mask_sa(struct brw_compile *p, int dispatch_width);
16 bool brw_wm_kernel__affine_opacity(struct brw_compile *p, int dispatch_width);
17 bool brw_wm_kernel__projective_opacity(struct brw_compile *p, int dispatch_width);
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/intel/compiler/
brw_fs_builder.h 53 * \p dispatch_width gives the native execution width of the program.
56 unsigned dispatch_width) :
58 _dispatch_width(dispatch_width),
119 if (n <= dispatch_width() && i < dispatch_width() / n) {
178 dispatch_width() const function in class:brw::fs_builder
195 * dispatch_width units (which is just enough space for one logical
201 assert(dispatch_width() <= 32);
205 DIV_ROUND_UP(n * type_sz(type) * dispatch_width(),
260 return emit(instruction(opcode, dispatch_width()));
    [all...]
brw_vec4_builder.h 54 vec4_builder(backend_shader *shader, unsigned dispatch_width = 8) :
56 _dispatch_width(dispatch_width), _group(0),
114 (n <= dispatch_width() && i < dispatch_width() / n));
151 dispatch_width() const function in class:brw::vec4_builder
168 * dispatch_width units (which is just enough space for four logical
174 assert(dispatch_width() <= 32);
190 return dst_reg(retype(brw_null_vec(dispatch_width()),
200 return dst_reg(retype(brw_null_vec(dispatch_width()),
210 return dst_reg(retype(brw_null_vec(dispatch_width()),
    [all...]
brw_fs_visitor.cpp 96 int reg_width = dispatch_width / 8;
181 for (unsigned i = 0; i < dispatch_width / 8; i++) {
345 abld.exec_all().group(MIN2(16, dispatch_width) * 2, 0);
381 for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) {
382 const fs_builder hbld = abld.group(MIN2(16, dispatch_width), i);
387 abld.exec_all().group(hbld.dispatch_width() * 2, 0);
408 } else if (devinfo->ver >= 8 || dispatch_width == 8) {
420 abld.exec_all().group(hbld.dispatch_width() * 2, 0);
529 for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) {
545 for (unsigned q = 0; q < dispatch_width / 8; q++)
    [all...]
brw_fs.h 78 return offset(reg, bld.dispatch_width(), delta);
99 unsigned dispatch_width,
423 const unsigned dispatch_width; /**< 8, 16 or 32 */ member in class:fs_visitor
476 int generate_code(const cfg_t *cfg, int dispatch_width,
577 unsigned dispatch_width; /**< 8, 16 or 32 */ member in class:fs_generator
595 if (bld.dispatch_width() > 16) {
598 const unsigned m = bld.dispatch_width() / hbld.dispatch_width();
622 const unsigned m = bld.dispatch_width() / hbld.dispatch_width();
    [all...]
brw_fs_reg_allocate.cpp 50 int reg_width = dispatch_width / 8;
80 aligned_bary_size(unsigned dispatch_width)
82 return (dispatch_width == 8 ? 2 : 4);
86 brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
90 const int index = util_logbase2(dispatch_width / 8);
92 if (dispatch_width > 8 && devinfo->ver >= 7) {
133 if (devinfo->ver <= 5 && dispatch_width >= 16) {
156 (dispatch_width == 8 && devinfo->ver <= 5))) {
157 int contig_len = aligned_bary_size(dispatch_width);
310 * (dispatch_width == 8). In extending to SIMD16, the code wa
    [all...]
brw_wm_iz.cpp 125 assert(dispatch_width <= 16);
brw_compiler.h 1067 unsigned dispatch_width)
1069 assert(dispatch_width == 8 ||
1070 dispatch_width == 16 ||
1071 dispatch_width == 32);
1072 const unsigned index = dispatch_width / 16;
1468 uint32_t dispatch_width; /**< 0 for vec4 */ member in struct:brw_compile_stats
brw_fs_nir.cpp 46 last_scratch = ALIGN(nir->scratch_size, 4) * dispatch_width;
222 for (unsigned i = 0; i < DIV_ROUND_UP(v->dispatch_width, 16); i++) {
223 const fs_builder hbld = abld.group(MIN2(16, v->dispatch_width), i);
289 if (dispatch_width > 8)
291 if (dispatch_width > 16) {
3818 workgroup_size() <= dispatch_width) {
3863 inst->size_written = 3 * dispatch_width * 4;
3909 inst->size_written = instr->num_components * dispatch_width * 4;
4169 const unsigned chan_index_bits = ffs(dispatch_width) - 1;
4312 inst->size_written = instr->num_components * dispatch_width * 4
    [all...]
brw_fs.cpp 661 if (dispatch_width == 8)
681 dispatch_width, stage_abbrev, msg);
714 if (dispatch_width > n) {
1199 int reg_width = dispatch_width / 8;
1456 for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) {
1457 const fs_builder hbld = abld.group(MIN2(16, dispatch_width), i);
3559 if (dispatch_width >= 16)
4078 fs_reg imm(VGRF, alloc.allocate(dispatch_width / 8), inst->dst.type);
4512 * thread payload, \p bld is required to have a dispatch_width() not greater
4523 assert(bld.dispatch_width() <= 16)
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
brw_fs_builder.h 53 * \p dispatch_width gives the native execution width of the program.
56 unsigned dispatch_width) :
58 _dispatch_width(dispatch_width),
119 if (n <= dispatch_width() && i < dispatch_width() / n) {
178 dispatch_width() const function in class:brw::fs_builder
195 * dispatch_width units (which is just enough space for one logical
201 assert(dispatch_width() <= 32);
205 DIV_ROUND_UP(n * type_sz(type) * dispatch_width(),
257 assert(shader->devinfo->gen >= 6 && dispatch_width() <= 16)
    [all...]
brw_nir_lower_cs_intrinsics.c 29 unsigned dispatch_width; member in struct:lower_intrinsics_state
65 if (state->local_workgroup_size <= state->dispatch_width)
71 nir_imul_imm(b, subgroup_id, state->dispatch_width);
159 DIV_ROUND_UP(local_workgroup_size, state->dispatch_width);
192 unsigned dispatch_width)
198 .dispatch_width = dispatch_width,
brw_vec4_builder.h 54 vec4_builder(backend_shader *shader, unsigned dispatch_width = 8) :
56 _dispatch_width(dispatch_width), _group(0),
114 (n <= dispatch_width() && i < dispatch_width() / n));
151 dispatch_width() const function in class:brw::vec4_builder
168 * dispatch_width units (which is just enough space for four logical
174 assert(dispatch_width() <= 32);
190 return dst_reg(retype(brw_null_vec(dispatch_width()),
200 return dst_reg(retype(brw_null_vec(dispatch_width()),
210 return dst_reg(retype(brw_null_vec(dispatch_width()),
    [all...]
brw_fs_visitor.cpp 96 int reg_width = dispatch_width / 8;
179 if (devinfo->has_pln && dispatch_width == 16) {
212 for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) {
213 const fs_builder hbld = abld.group(MIN2(16, dispatch_width), i);
216 if (devinfo->gen >= 8 || dispatch_width == 8) {
228 abld.exec_all().group(hbld.dispatch_width() * 2, 0);
286 for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) {
298 for (unsigned q = 0; q < dispatch_width / 8; q++) {
300 const unsigned idx = c + (q & 2) + (q & 1) * dispatch_width / 8;
976 unsigned dispatch_width,
    [all...]
brw_fs_reg_allocate.cpp 49 int reg_width = dispatch_width / 8;
76 brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
80 const int index = _mesa_logbase2(dispatch_width / 8);
82 if (dispatch_width > 8 && devinfo->gen >= 7) {
118 if (devinfo->gen <= 5 && dispatch_width >= 16) {
165 if (devinfo->gen <= 5 && dispatch_width >= 16) {
211 if (devinfo->gen <= 5 && dispatch_width >= 16) {
252 if (devinfo->has_pln && dispatch_width == 8 && devinfo->gen <= 6) {
447 if (devinfo->gen <= 5 && dispatch_width >= 16) {
471 int reg_width = v->dispatch_width / 8
    [all...]
brw_fs.h 50 return offset(reg, bld.dispatch_width(), delta);
69 unsigned dispatch_width,
387 const unsigned dispatch_width; /**< 8, 16 or 32 */ member in class:fs_visitor
422 int generate_code(const cfg_t *cfg, int dispatch_width);
517 unsigned dispatch_width; /**< 8, 16 or 32 */ member in class:fs_generator
536 if (bld.dispatch_width() > 16) {
539 const unsigned m = bld.dispatch_width() / hbld.dispatch_width();
brw_nir.h 104 unsigned dispatch_width);
brw_wm_iz.cpp 125 assert(dispatch_width <= 16);
brw_fs.cpp 666 if (dispatch_width == 8)
718 if (dispatch_width > n) {
1104 return 1 * dispatch_width / 8;
1108 return 2 * dispatch_width / 8;
1140 int reg_width = dispatch_width / 8;
1389 for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 16); i++) {
1390 const fs_builder hbld = abld.group(MIN2(16, dispatch_width), i);
2818 if (stage != MESA_SHADER_FRAGMENT || dispatch_width > 16)
3435 if (dispatch_width >= 16)
3883 for (unsigned i = 0; i < DIV_ROUND_UP(dispatch_width, 8); i++)
    [all...]
brw_fs_nir.cpp 196 for (unsigned i = 0; i < DIV_ROUND_UP(v->dispatch_width, 16); i++) {
197 const fs_builder hbld = abld.group(MIN2(16, v->dispatch_width), i);
257 if (dispatch_width > 8)
259 if (dispatch_width > 16) {
3770 inst->size_written = instr->num_components * dispatch_width * 4;
4022 inst->size_written = instr->num_components * dispatch_width * 4;
4150 inst->size_written = instr->num_components * dispatch_width * 4;
4471 inst->size_written = instr->num_components * dispatch_width * 4;
4662 if (dispatch_width == 32) {
4679 set_predicate(dispatch_width == 8 ? BRW_PREDICATE_ALIGN1_ANY8H
    [all...]

Completed in 40 milliseconds

1 2