| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/ir3/ |
| ir3_cache.h | 42 struct ir3_shader_state *vs, *hs, *ds, *gs, *fs; // 5 pointers member in struct:ir3_cache_key
62 struct ir3_shader_variant *vs, struct ir3_shader_variant *hs,
|
| ir3_cache.c | 100 if (key->hs)
105 [MESA_SHADER_TESS_CTRL] = ir3_get_shader(key->hs),
183 (key->hs == stobj) || (key->gs == stobj)) {
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a6xx/ |
| fd6_program.h | 43 struct ir3_shader_variant *hs; member in struct:fd6_program_state
|
| fd6_const.c | 147 /* VS sizes are in bytes since that's what STLW/LDLW use, while the HS
150 unsigned num_vertices = emit->hs
161 if (emit->hs) {
165 emit->hs->output_size, emit->patch_vertices};
167 emit_stage_tess_consts(constobj, emit->hs, hs_params,
169 emit_tess_bos(constobj, emit, emit->hs);
177 emit->hs->output_size, /* hs vertex stride (dwords) */
178 emit->hs->shader->nir->info.tess.tcs_vertices_out};
290 emit->vs, emit->hs, emit->ds, emit->gs, emit->fs
[all...] |
| fd6_program.c | 290 OUT_RING(ring, COND(state->hs,
292 A6XX_HLSQ_HS_CNTL_CONSTLEN(state->hs->constlen)));
310 OUT_RING(ring, COND(state->hs,
312 A6XX_SP_HS_CONFIG_NIBO(ir3_shader_nibo(state->hs)) |
313 A6XX_SP_HS_CONFIG_NTEX(state->hs->num_samp) |
314 A6XX_SP_HS_CONFIG_NSAMP(state->hs->num_samp)));
376 const struct ir3_shader_variant *hs = state->hs; variable in typeref:struct:ir3_shader_variant
398 if (hs)
399 vs_primitive_regid = ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID)
[all...] |
| fd6_draw.c | 172 emit.key.hs = ctx->prog.hs;
175 if (!(ctx->prog.hs && ctx->prog.ds))
194 if (!(emit.key.hs || emit.key.ds || emit.key.gs || indirect))
217 emit.hs = fd6_emit_get_prog(&emit)->hs;
231 ctx->stats.hs_regs += COND(emit.hs, ir3_shader_halfregs(emit.hs));
297 MAX2(ctx->batch->tessparam_size, emit.hs->output_size * 4 * count);
|
| fd6_emit.c | 820 if (emit->hs) {
821 debug_assert(ir3_shader_nibo(emit->hs) == 0);
1007 const struct ir3_shader_variant *hs = emit->hs; local
1102 if (hs) {
1104 ring, emit, PIPE_SHADER_TESS_CTRL, hs);
|
| fd6_emit.h | 110 struct ir3_shader_variant *hs; member in struct:fd6_emit
|
| /xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/ |
| genX_pipeline.c | 1402 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_HS), hs);
1417 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_HS), hs) {
1418 hs.Enable = true;
1419 hs.StatisticsEnable = true;
1420 hs.KernelStartPointer = tcs_bin->kernel.offset;
1422 hs.SamplerCount = GEN_GEN == 11 ? 0 : get_sampler_count(tcs_bin);
1424 hs.BindingTableEntryCount = GEN_GEN == 11 ? 0 : get_binding_table_entry_count(tcs_bin);
1425 hs.MaximumNumberofThreads = devinfo->max_tcs_threads - 1;
1426 hs.IncludeVertexHandles = true;
1427 hs.InstanceCount = tcs_prog_data->instances - 1
[all...] |
| genX_gpu_memcpy.c | 120 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_HS), hs);
|
| /xsrc/external/mit/MesaLib/dist/src/freedreno/vulkan/ |
| tu_pipeline.c | 673 const struct ir3_shader_variant *hs,
682 const uint32_t tess_coord_x_regid = hs ?
688 const uint32_t hs_rel_patch_regid = hs ?
689 ir3_find_sysval_regid(hs, SYSTEM_VALUE_REL_PATCH_ID_IR3) :
691 const uint32_t ds_rel_patch_regid = hs ?
694 const uint32_t hs_invocation_regid = hs ?
695 ir3_find_sysval_regid(hs, SYSTEM_VALUE_TCS_HEADER_IR3) :
700 const uint32_t vs_primitiveid_regid = hs ?
701 ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID) :
893 const struct ir3_shader_variant *hs,
1642 const struct ir3_shader_variant *hs = builder->variants[MESA_SHADER_TESS_CTRL]; local
2715 const struct ir3_shader_variant *hs = builder->variants[MESA_SHADER_TESS_CTRL]; local
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/intel/vulkan/ |
| genX_pipeline.c | 1849 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_HS), hs);
1864 anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_HS), hs) {
1865 hs.Enable = true;
1866 hs.StatisticsEnable = true;
1867 hs.KernelStartPointer = tcs_bin->kernel.offset;
1869 hs.SamplerCount = GFX_VER == 11 ? 0 : get_sampler_count(tcs_bin);
1870 hs.BindingTableEntryCount = tcs_bin->bind_map.surface_count;
1882 hs.MaximumNumberofThreads = devinfo->max_tcs_threads - 1;
1883 hs.IncludeVertexHandles = true;
1884 hs.InstanceCount = tcs_prog_data->instances - 1
[all...] |
| genX_gpu_memcpy.c | 131 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_HS), hs);
|
| /xsrc/external/mit/xf86-video-mga/dist/src/ |
| mga_dac3026.c | 485 int hd, hs, he, ht, vd, vs, ve, vt, wd; local
564 hs = (mode->CrtcHSyncStart >> 3) - 1;
589 pReg->ExtVga[5] = (hs + he - ht) >> 1;
600 ((hs & 0x100) >> 6) |
621 pVga->CRTC[4] = hs;
|
| mga_dacG.c | 1133 int hd, hs, he, ht, vd, vs, ve, vt, wd; local
1364 hs = (mode->CrtcHSyncStart >> 3) - 1;
1389 pReg->ExtVga[5] = (hs + he - ht) >> 1;
1397 ((hs & 0x100) >> 6) |
1420 pVga->CRTC[4] = hs;
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/ |
| freedreno_program.c | 67 ctx->prog.hs = hwcso;
|
| freedreno_blitter.c | 85 util_blitter_save_tessctrl_shader(ctx->blitter, ctx->prog.hs);
|
| freedreno_context.h | 64 void *vs, *hs, *ds, *gs, *fs; member in struct:fd_program_stateobj
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/ |
| si_state_draw.cpp | 131 si_pm4_bind_state(sctx, hs, sctx->shader.tcs.current);
146 si_pm4_bind_state(sctx, hs, sctx->fixed_func_tcs_shader.current);
169 si_pm4_bind_state(sctx, hs, NULL);
222 sctx->vs_uses_base_instance = sctx->queued.named.hs->uses_base_instance;
309 si_pm4_state_enabled_and_changed(sctx, hs) || si_pm4_state_enabled_and_changed(sctx, gs) ||
317 scratch_size = MAX2(scratch_size, sctx->queued.named.hs->config.scratch_bytes_per_wave);
345 if (HAS_TESS && si_pm4_state_enabled_and_changed(sctx, hs))
422 si_prefetch_shader_async(sctx, sctx->queued.named.hs);
465 si_prefetch_shader_async(sctx, sctx->queued.named.hs);
523 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. *
[all...] |
| si_state.h | 187 struct si_shader *hs; member in struct:si_state::si_state_named
|
| /xsrc/external/mit/MesaLib.old/dist/src/freedreno/vulkan/ |
| tu_pipeline.c | 388 tu6_emit_hs_config(struct tu_cs *cs, const struct ir3_shader_variant *hs)
391 if (hs->instrlen)
399 tu_cs_emit(cs, hs->instrlen);
402 tu_cs_emit(cs, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(hs->constlen, 4)));
900 const struct ir3_shader_variant *hs = local
923 tu6_emit_hs_config(cs, hs);
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/ |
| si_cp_dma.c | 456 cik_prefetch_shader_async(sctx, sctx->queued.named.hs);
508 cik_prefetch_shader_async(sctx, sctx->queued.named.hs);
|
| si_state.h | 159 struct si_pm4_state *hs; member in struct:si_state::__anon4064
|
| si_state_shaders.c | 415 * TES as VS | LS -> HS -> VS | 14 or 30
416 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
1484 /* The LS output / HS input layout can be communicated
1485 * directly instead of via user SGPRs for merged LS-HS.
2696 si_pm4_delete_state(sctx, hs, shader->pm4);
3147 si_pm4_bind_state(sctx, hs, tcs->pm4);
3371 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3384 si_pm4_bind_state(sctx, hs,
3415 si_pm4_bind_state(sctx, hs, NULL);
3424 si_pm4_bind_state(sctx, hs, NULL)
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a3xx/ |
| fd3_program.c | 454 struct ir3_shader_variant *vs, struct ir3_shader_variant *hs,
|
