Searched refs:rsrc2 (Results 1 - 18 of 18) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_binary.h49 unsigned rsrc2; member in struct:ac_shader_config
H A Dac_binary.c68 conf->rsrc2 = value;
72 conf->rsrc2 = value;
76 conf->rsrc2 = value;
80 conf->rsrc2 = value;
84 conf->rsrc2 = value;
H A Dac_rtld.c556 assert(config->rsrc1 == 0 && config->rsrc2 == 0);
558 config->rsrc2 = c.rsrc2;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_compute.c72 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32; local in function:code_object_to_config
77 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
78 out_config->rsrc2 = rsrc2;
174 shader->config.rsrc2 =
451 config->rsrc2 &= C_00B84C_LDS_SIZE;
452 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
498 radeon_emit(cs, config->rsrc2);
501 "COMPUTE_PGM_RSRC2: 0x%08x\n", config->rsrc1, config->rsrc2);
H A Dsi_shader.h575 unsigned rsrc2; member in struct:si_shader_config
H A Dsi_state_draw.c255 unsigned hs_rsrc2 = ls_current->config.rsrc2 |
268 unsigned ls_rsrc2 = ls_current->config.rsrc2;
H A Dsi_state_shaders.c499 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
529 shader->config.rsrc2 =
537 shader->config.rsrc2 =
552 shader->config.rsrc2);
H A Dsi_shader.c5111 conf->rsrc2 = value;
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_pipeline_cache.c37 uint32_t rsrc1, rsrc2; member in struct:cache_entry_variant_info
328 variant->rsrc2 = info.rsrc2;
417 info.rsrc2 = variants[i]->rsrc2;
H A Dradv_shader.c460 variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
477 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
483 variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
493 variant->rsrc2 |=
534 variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
H A Dradv_shader.h317 unsigned rsrc2; member in struct:radv_shader_variant
H A Dradv_pipeline.c2969 radeon_emit(cs, shader->rsrc2);
3028 radeon_emit(cs, shader->rsrc2);
3038 uint32_t rsrc2 = shader->rsrc2; local in function:radv_pipeline_generate_hw_ls
3044 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3047 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3051 radeon_emit(cs, rsrc2);
3069 radeon_emit(cs, shader->rsrc2 |
3076 radeon_emit(cs, shader->rsrc2);
3195 radeon_emit(cs, gs->rsrc2 | S_00B22C_LDS_SIZ
[all...]
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_shader.c1350 config_out->rsrc2 = S_00B12C_USER_SGPR(info->num_user_sgprs) |
1361 config_out->rsrc2 |=
1371 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(info->num_user_sgprs >> 5);
1374 config_out->rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(info->num_user_sgprs >> 5);
1383 config_out->rsrc2 |= S_00B22C_OC_LDS_EN(1) | S_00B22C_EXCP_EN(excp_en);
1388 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1) | S_00B12C_EXCP_EN(excp_en);
1394 config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1) | S_00B12C_EXCP_EN(excp_en);
1396 config_out->rsrc2 |= S_00B22C_SHARED_VGPR_CNT(num_shared_vgpr_blocks);
1406 config_out->rsrc2 |=
1410 config_out->rsrc2 |
[all...]
H A Dradv_pipeline.c4408 radeon_emit(cs, shader->config.rsrc2);
4481 radeon_emit(cs, shader->config.rsrc2);
4490 uint32_t rsrc2 = shader->config.rsrc2; local in function:radv_pipeline_generate_hw_ls
4494 rsrc2 |= S_00B52C_LDS_SIZE(num_lds_blocks);
4497 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
4501 radeon_emit(cs, rsrc2);
4521 radeon_emit(cs, shader->config.rsrc2);
4660 radeon_emit(cs, shader->config.rsrc2);
4666 radeon_emit(cs, shader->config.rsrc2);
[all...]
H A Dradv_cmd_buffer.c1375 (v->config.rsrc2 & C_00B22C_LDS_SIZE) |
6513 uint32_t rsrc2 = v->config.rsrc2; local in function:radv_emit_ngg_culling_state
6518 rsrc2 = (rsrc2 & C_00B22C_LDS_SIZE) | S_00B22C_LDS_SIZE(v->info.num_lds_blocks_when_not_culling);
6526 radeon_set_sh_reg(cmd_buffer->cs, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_compute.c98 uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32; local in function:code_object_to_config
103 out_config->lds_size = MAX2(out_config->lds_size, G_00B84C_LDS_SIZE(rsrc2));
104 out_config->rsrc2 = rsrc2;
207 shader->config.rsrc2 = S_00B84C_USER_SGPR(user_sgprs) | S_00B84C_SCRATCH_EN(scratch_enabled) |
512 config->rsrc2 &= C_00B84C_LDS_SIZE;
513 config->rsrc2 |= S_00B84C_LDS_SIZE(lds_blocks);
545 radeon_emit(config->rsrc2);
550 config->rsrc1, config->rsrc2);
H A Dsi_state_shaders.c546 shader->config.rsrc2 =
571 shader->config.rsrc2 = S_00B42C_USER_SGPR(num_user_sgprs) |
575 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
577 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
583 shader->config.rsrc2 = S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) | S_00B42C_OC_LDS_EN(1) |
600 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, shader->config.rsrc2);
928 uint32_t rsrc2 = S_00B22C_USER_SGPR(num_user_sgprs) | local in function:si_shader_gs
935 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
938 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
942 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
1518 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) | S_00B12C_OC_LDS_EN(oc_lds_en) | local in function:si_shader_vs
[all...]
H A Dsi_state_draw.cpp714 unsigned hs_rsrc2 = ls_current->config.rsrc2;
730 unsigned ls_rsrc2 = ls_current->config.rsrc2;

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