Searched refs:si_pm4_set_reg (Results 1 - 8 of 8) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_pm4.h62 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val);
H A Dsi_state.c470 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
476 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
512 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
522 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
532 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
588 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
624 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4, sx_mrt_blend_opt[i]);
631 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
988 si_pm4_set_reg(
999 si_pm4_set_reg(pm
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H A Dsi_state_shaders.c540 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
564 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
566 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
579 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
580 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS,
587 si_pm4_set_reg(
600 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, shader->config.rsrc2);
654 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
655 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES,
657 si_pm4_set_reg(pm
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H A Dsi_pm4.c51 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val) function in typeref:typename:void
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_pm4.h72 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val);
H A Dsi_state.c475 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
513 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
524 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
534 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
598 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
631 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
640 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
889 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
900 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
913 si_pm4_set_reg(pm
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H A Dsi_state_shaders.c491 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
492 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
517 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
518 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
534 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
535 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
543 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
551 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
612 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
613 si_pm4_set_reg(pm
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H A Dsi_pm4.c50 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val) function in typeref:typename:void

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