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Searched refs:sps_info_flags (Results 1 - 12 of 12) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeon/
H A D	radeon_vcn_dec.c	86 result.sps_info_flags = 0; 87 result.sps_info_flags \|= pic->pps->sps->direct_8x8_inference_flag << 0; 88 result.sps_info_flags \|= pic->pps->sps->mb_adaptive_frame_field_flag << 1; 89 result.sps_info_flags \|= pic->pps->sps->frame_mbs_only_flag << 2; 90 result.sps_info_flags \|= pic->pps->sps->delta_pic_order_always_zero_flag << 3; 91 result.sps_info_flags \|= 1 << RDECODE_SPS_INFO_H264_EXTENSION_SUPPORT_FLAG_SHIFT; 169 result.sps_info_flags = 0; 170 result.sps_info_flags \|= pic->pps->sps->scaling_list_enabled_flag << 0; 171 result.sps_info_flags \|= pic->pps->sps->amp_enabled_flag << 1; 172 result.sps_info_flags \| [all...]
H A D	radeon_uvd.c	519 result.sps_info_flags = 0; 520 result.sps_info_flags \|= pic->pps->sps->direct_8x8_inference_flag << 0; 521 result.sps_info_flags \|= pic->pps->sps->mb_adaptive_frame_field_flag << 1; 522 result.sps_info_flags \|= pic->pps->sps->frame_mbs_only_flag << 2; 523 result.sps_info_flags \|= pic->pps->sps->delta_pic_order_always_zero_flag << 3; 599 result.sps_info_flags = 0; 600 result.sps_info_flags \|= pic->pps->sps->scaling_list_enabled_flag << 0; 601 result.sps_info_flags \|= pic->pps->sps->amp_enabled_flag << 1; 602 result.sps_info_flags \|= pic->pps->sps->sample_adaptive_offset_enabled_flag << 2; 603 result.sps_info_flags \| [all...]
H A D	radeon_uvd.h	`136 uint32_t sps_info_flags; member in struct:ruvd_h264 185 uint32_t sps_info_flags; member in struct:ruvd_h265 256 uint32_t sps_info_flags; member in struct:ruvd_vc1`
H A D	radeon_vcn_dec.h	`316 unsigned int sps_info_flags; member in struct:rvcn_dec_message_avc_s 366 unsigned int sps_info_flags; member in struct:rvcn_dec_message_vc1_s 498 unsigned int sps_info_flags; member in struct:rvcn_dec_message_hevc_s`
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeon/
H A D	radeon_uvd.c	514 result.sps_info_flags = 0; 515 result.sps_info_flags \|= pic->pps->sps->direct_8x8_inference_flag << 0; 516 result.sps_info_flags \|= pic->pps->sps->mb_adaptive_frame_field_flag << 1; 517 result.sps_info_flags \|= pic->pps->sps->frame_mbs_only_flag << 2; 518 result.sps_info_flags \|= pic->pps->sps->delta_pic_order_always_zero_flag << 3; 594 result.sps_info_flags = 0; 595 result.sps_info_flags \|= pic->pps->sps->scaling_list_enabled_flag << 0; 596 result.sps_info_flags \|= pic->pps->sps->amp_enabled_flag << 1; 597 result.sps_info_flags \|= pic->pps->sps->sample_adaptive_offset_enabled_flag << 2; 598 result.sps_info_flags \| [all...]
H A D	radeon_uvd.h	`138 uint32_t sps_info_flags; member in struct:ruvd_h264 187 uint32_t sps_info_flags; member in struct:ruvd_h265 258 uint32_t sps_info_flags; member in struct:ruvd_vc1`
H A D	radeon_vcn_dec.c	105 result.sps_info_flags = 0; 106 result.sps_info_flags \|= pic->pps->sps->direct_8x8_inference_flag << 0; 107 result.sps_info_flags \|= pic->pps->sps->mb_adaptive_frame_field_flag << 1; 108 result.sps_info_flags \|= pic->pps->sps->frame_mbs_only_flag << 2; 109 result.sps_info_flags \|= pic->pps->sps->delta_pic_order_always_zero_flag << 3; 110 result.sps_info_flags \|= 1 << RDECODE_SPS_INFO_H264_EXTENSION_SUPPORT_FLAG_SHIFT; 187 result.sps_info_flags = 0; 188 result.sps_info_flags \|= pic->pps->sps->scaling_list_enabled_flag << 0; 189 result.sps_info_flags \|= pic->pps->sps->amp_enabled_flag << 1; 190 result.sps_info_flags \| [all...]
H A D	radeon_vcn_dec.h	`504 unsigned int sps_info_flags; member in struct:rvcn_dec_message_avc_s 554 unsigned int sps_info_flags; member in struct:rvcn_dec_message_vc1_s 686 unsigned int sps_info_flags; member in struct:rvcn_dec_message_hevc_s`
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A D	radeon_uvd.c	463 result.sps_info_flags = 0; 464 result.sps_info_flags \|= pic->pps->sps->direct_8x8_inference_flag << 0; 465 result.sps_info_flags \|= pic->pps->sps->mb_adaptive_frame_field_flag << 1; 466 result.sps_info_flags \|= pic->pps->sps->frame_mbs_only_flag << 2; 467 result.sps_info_flags \|= pic->pps->sps->delta_pic_order_always_zero_flag << 3; 543 result.sps_info_flags = 0; 544 result.sps_info_flags \|= pic->pps->sps->scaling_list_enabled_flag << 0; 545 result.sps_info_flags \|= pic->pps->sps->amp_enabled_flag << 1; 546 result.sps_info_flags \|= pic->pps->sps->sample_adaptive_offset_enabled_flag << 2; 547 result.sps_info_flags \| [all...]
H A D	radeon_uvd.h	`137 uint32_t sps_info_flags; member in struct:ruvd_h264 186 uint32_t sps_info_flags; member in struct:ruvd_h265 257 uint32_t sps_info_flags; member in struct:ruvd_vc1`
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A D	radeon_uvd.h	`137 uint32_t sps_info_flags; member in struct:ruvd_h264 186 uint32_t sps_info_flags; member in struct:ruvd_h265 257 uint32_t sps_info_flags; member in struct:ruvd_vc1`
H A D	radeon_uvd.c	398 result.sps_info_flags = 0; 399 result.sps_info_flags \|= pic->pps->sps->direct_8x8_inference_flag << 0; 400 result.sps_info_flags \|= pic->pps->sps->mb_adaptive_frame_field_flag << 1; 401 result.sps_info_flags \|= pic->pps->sps->frame_mbs_only_flag << 2; 402 result.sps_info_flags \|= pic->pps->sps->delta_pic_order_always_zero_flag << 3; 497 result.sps_info_flags \|= pic->postprocflag << 7; 498 result.sps_info_flags \|= pic->pulldown << 6; 499 result.sps_info_flags \|= pic->interlace << 5; 500 result.sps_info_flags \|= pic->tfcntrflag << 4; 501 result.sps_info_flags \| [all...]

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