| /xsrc/external/mit/MesaLib/dist/src/amd/common/ |
| H A D | ac_surface_test_common.h | 44 info->tcc_cache_line_size = 64;
59 info->tcc_cache_line_size = 64;
75 info->tcc_cache_line_size = 64;
90 info->tcc_cache_line_size = 64;
105 info->tcc_cache_line_size = 128;
120 info->tcc_cache_line_size = 128;
135 info->tcc_cache_line_size = 128;
152 info->tcc_cache_line_size = 128;
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| H A D | ac_gpu_info.h | 116 uint32_t tcc_cache_line_size; member in struct:radeon_info
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| H A D | ac_gpu_info.c | 748 info->tcc_cache_line_size = 128;
760 info->tcc_cache_line_size = 128;
762 info->tcc_cache_line_size = 64;
999 ib_align = MAX2(ib_align, info->tcc_cache_line_size);
1194 fprintf(f, " tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
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| /xsrc/external/mit/MesaLib.old/dist/src/amd/common/ |
| H A D | ac_gpu_info.h | 62 uint32_t tcc_cache_line_size; member in struct:radeon_info
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| H A D | ac_gpu_info.c | 411 info->tcc_cache_line_size = 64; /* TC L2 line size on GCN */
516 printf(" tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
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| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/ |
| H A D | si_pipe.h | 1539 unsigned alignment, tcc_cache_line_size; local in function:si_optimal_tcc_alignment
1547 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1548 return MIN2(alignment, tcc_cache_line_size);
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| H A D | si_buffer.c | 476 sctx->screen->info.tcc_cache_line_size,
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| H A D | si_compute.c | 672 sctx->screen->info.tcc_cache_line_size,
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| H A D | si_pipe.c | 571 sctx->screen->info.tcc_cache_line_size);
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| H A D | si_state_draw.c | 1405 sctx->screen->info.tcc_cache_line_size,
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| H A D | si_texture.c | 1313 align64(tex->size, sscreen->info.tcc_cache_line_size);
1429 sscreen->info.tcc_cache_line_size);
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/ |
| H A D | si_pipe.h | 1716 unsigned alignment, tcc_cache_line_size; local in function:si_optimal_tcc_alignment
1724 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1725 return MIN2(alignment, tcc_cache_line_size);
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| H A D | si_pipe.c | 657 sscreen->info.tcc_cache_line_size);
667 sscreen->info.tcc_cache_line_size);
680 sctx->screen->info.tcc_cache_line_size);
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| H A D | si_buffer.c | 428 sctx->screen->info.tcc_cache_line_size, &offset,
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| H A D | si_compute.c | 699 sctx->screen->info.tcc_cache_line_size, &kernel_args_offset,
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| H A D | si_state_draw.cpp | 2179 sctx->screen->info.tcc_cache_line_size,
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| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/ |
| H A D | r600_buffer_common.c | 421 rctx->screen->info.tcc_cache_line_size,
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| H A D | r600_pipe_common.c | 186 rctx->screen->info.tcc_cache_line_size,
1357 printf("tcc_cache_line_size = %u\n", rscreen->info.tcc_cache_line_size);
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/ |
| H A D | r600_buffer_common.c | 423 rctx->screen->info.tcc_cache_line_size,
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| H A D | r600_pipe_common.c | 163 rctx->screen->info.tcc_cache_line_size,
1300 printf("tcc_cache_line_size = %u\n", rscreen->info.tcc_cache_line_size);
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| /xsrc/external/mit/MesaLib.old/dist/src/gallium/winsys/radeon/drm/ |
| H A D | radeon_drm_winsys.c | 567 ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
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| /xsrc/external/mit/MesaLib/dist/src/gallium/winsys/radeon/drm/ |
| H A D | radeon_drm_winsys.c | 580 ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
|