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  /xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
brw_nir.h 109 void brw_nir_lower_tes_inputs(nir_shader *nir, const struct brw_vue_map *vue);
114 void brw_nir_lower_tcs_outputs(nir_shader *nir, const struct brw_vue_map *vue,
brw_compiler.h 262 * the VUE, even if they aren't written by the vertex shader.
738 /* Mapping of VUE slots to interpolation modes.
877 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
903 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
904 * single octaword within the VUE (128 bits).
907 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
908 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
909 * in a vertex shader), each register corresponds to a single VUE slot, since
914 * Bitfield representing all varying slots that are (a) stored in this VUE
1176 struct brw_vue_prog_data vue; member in union:brw_any_prog_data
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  /xsrc/external/mit/MesaLib/dist/src/intel/compiler/
brw_nir.h 112 void brw_nir_lower_tes_inputs(nir_shader *nir, const struct brw_vue_map *vue);
117 void brw_nir_lower_tcs_outputs(nir_shader *nir, const struct brw_vue_map *vue,
brw_compiler.h 331 * the VUE, even if they aren't written by the vertex shader.
917 /* Mapping of VUE slots to interpolation modes.
1112 * compile_sf_prog() inserts into its VUE map to cause the gl_PointCoord
1138 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a
1139 * single octaword within the VUE (128 bits).
1142 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two
1143 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as
1144 * in a vertex shader), each register corresponds to a single VUE slot, since
1149 * Bitfield representing all varying slots that are (a) stored in this VUE
1422 struct brw_vue_prog_data vue; member in union:brw_any_prog_data
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  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/iris/
iris_context.h 222 struct iris_vue_prog_key vue; member in struct:iris_vs_prog_key
226 struct iris_vue_prog_key vue; member in struct:iris_tcs_prog_key
242 struct iris_vue_prog_key vue; member in struct:iris_tes_prog_key
252 struct iris_vue_prog_key vue; member in struct:iris_gs_prog_key
278 struct iris_vue_prog_key vue; member in union:iris_any_prog_key
504 * (the VUE-based information for transform feedback outputs).
iris_program.c 103 BRW_KEY_INIT(devinfo->ver, key->vue.base.program_string_id),
117 BRW_KEY_INIT(devinfo->ver, key->vue.base.program_string_id),
131 BRW_KEY_INIT(devinfo->ver, key->vue.base.program_string_id),
142 BRW_KEY_INIT(devinfo->ver, key->vue.base.program_string_id),
395 * but the layout is defined by the VUE map, which we won't have until we
400 * components of our VUE header. See brw_vue_map.c for the layout.
418 /* The VUE header contains three scalar fields packed together:
1321 if (key->vue.nr_userclip_plane_consts) {
1323 nir_lower_clip_vs(nir, (1 << key->vue.nr_userclip_plane_consts) - 1,
1399 struct iris_vs_prog_key key = { KEY_ID(vue.base) }
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iris_state.c 4040 /* Viewport and Layer are stored in the VUE header. We need to override
4095 * which is counted in 256-bit increments (two 128-bit VUE slots).
4101 /* If we are doing two-sided color, and the VUE slot following this one
4217 key->vue.nr_userclip_plane_consts = cso_rast->num_clip_plane_consts;
4243 key->vue.nr_userclip_plane_consts = cso_rast->num_clip_plane_consts;
4260 key->vue.nr_userclip_plane_consts = cso_rast->num_clip_plane_consts;
  /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
genX_state_upload.c 479 unsigned vue = brw->vb.nr_enabled; local
485 assert(vue > 0);
486 vue--;
489 WARN_ONCE(vue >= 33,
497 vfs.VertexIDElementOffset = vue;
503 vfs.InstanceIDElementOffset = vue;
509 vfi.VertexElementIndex = vue;
653 * of in the VUE. We have to upload it sideband as the last vertex
942 * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
946 * If an attribute is "swizzled", then the given VUE location is used fo
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  /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
genX_state_upload.c 485 unsigned vue = brw->vb.nr_enabled; local
491 assert(vue > 0);
492 vue--;
495 WARN_ONCE(vue >= 33,
503 vfs.VertexIDElementOffset = vue;
509 vfs.InstanceIDElementOffset = vue;
515 vfi.VertexElementIndex = vue;
660 * of in the VUE. We have to upload it sideband as the last vertex
952 * attribute in the VUE (relative to urb_entry_read_offset, see below), and a
956 * If an attribute is "swizzled", then the given VUE location is used fo
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  /xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
anv_pipeline.c 936 prev_stage->prog_data.vue.vue_map.slots_valid;
  /xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
anv_pipeline.c 1199 prev_stage->prog_data.vue.vue_map.slots_valid;

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