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  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
exynos5410.h 38 #define CLK_UART0 257
actions,s500-cmu.h 60 #define CLK_UART0 38
actions,s700-cmu.h 60 #define CLK_UART0 36
actions,s900-cmu.h 87 #define CLK_UART0 67
exynos5250.h 94 #define CLK_UART0 289
pistachio-clk.h 41 #define CLK_UART0 48
sophgo,cv1800.h 90 #define CLK_UART0 77
s5pv210.h 163 #define CLK_UART0 143
exynos3250.h 224 #define CLK_UART0 216
exynos4.h 152 #define CLK_UART0 312
exynos5420.h 68 #define CLK_UART0 257
sprd,sc9860-clk.h 87 #define CLK_UART0 2
  /src/sys/arch/mips/ingenic/
apbus.c 76 { "com", JZ_UART0, 51, CLK_UART0, 0, 0},
ingenic_regs.h 169 #define CLK_UART0 (1 << 15)
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/sprd/
whale2.dtsi 80 <&ap_clk CLK_UART0>, <&ext_26m>;
  /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/actions/
s700.dtsi 119 clocks = <&cmu CLK_UART0>;
s900.dtsi 125 clocks = <&cmu CLK_UART0>;
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
s5pv210.dtsi 323 clocks = <&clocks CLK_UART0>, <&clocks CLK_UART0>,
exynos5410.dtsi 344 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
owl-s500.dtsi 136 clocks = <&cmu CLK_UART0>;
exynos3250.dtsi 514 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
exynos4.dtsi 453 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
exynos5250.dtsi 1205 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
  /src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/sophgo/
cv18xx.dtsi 195 clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
  /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/img/
pistachio.dtsi 257 clocks = <&clk_core CLK_UART0>, <&cr_periph SYS_CLK_UART0>;

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