Searched refs:PIPE_CONTROL (Results 1 - 25 of 26) sorted by relevance

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/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dsna_reg.h69 #define PIPE_CONTROL BRW_3D(3, 2, 0) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dsna_reg.h69 #define PIPE_CONTROL BRW_3D(3, 2, 0) macro
/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A DgenX_query.c337 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
361 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
381 /* These queries are written with a PIPE_CONTROL so clear them using the
382 * PIPE_CONTROL as well so we don't have to synchronize between 2 types
530 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
546 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
587 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
605 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
659 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
742 /* Occlusion & timestamp queries are written using a PIPE_CONTROL an
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H A DgenX_state.c43 * markers in the pipeline by programming a PIPE_CONTROL with stall."
49 anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) {
69 anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) {
H A Dgen8_cmd_buffer.c113 /* According to the Broadwell PIPE_CONTROL documentation, software should
114 * emit a PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set
122 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
154 /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
161 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
H A DgenX_cmd_buffer.c68 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
171 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
172 * which, according the PIPE_CONTROL instruction documentation in the
180 * invalidation through a PIPE_CONTROL does nothing whatsoever in
190 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
861 * In order to work around this issue, we emit a PIPE_CONTROL with the
1092 * synchronized. The first PIPE_CONTROL here likely ensures that the
1428 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1441 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1445 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), p
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/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A DgenX_query.c611 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
638 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
658 /* These queries are written with a PIPE_CONTROL so clear them using the
659 * PIPE_CONTROL as well so we don't have to synchronize between 2 types
910 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
926 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
984 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1046 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1088 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1106 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), p
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H A DgenX_cmd_buffer.c55 convert_pc_to_bits(struct GENX(PIPE_CONTROL) *pc) {
107 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
118 * Software must program PIPE_CONTROL command with "HDC Pipeline
253 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
254 * which, according the PIPE_CONTROL instruction documentation in the
262 * invalidation through a PIPE_CONTROL does nothing whatsoever in
272 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
1111 * In order to work around this issue, we emit a PIPE_CONTROL with the
1472 * synchronized. The first PIPE_CONTROL here likely ensures that the
1884 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tell
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H A Dgfx8_cmd_buffer.c138 /* According to the Broadwell PIPE_CONTROL documentation, software should
139 * emit a PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set
147 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
154 /* Wa_1409600907: "PIPE_CONTROL with Depth Stall Enable bit must
155 * be set with any PIPE_CONTROL with Depth Flush Enable bit set.
187 /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
194 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D18.0.4.rst77 - i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL
H A D20.0.2.rst102 - anv: Use the PIPE_CONTROL instead of bits for the CS stall W/A
H A D21.3.7.rst131 - intel/genxml: add PIPE_CONTROL field for L3 read only cache invalidation
H A D19.1.0.rst3006 - iris: Allow PIPE_CONTROL with Stall at Scoreboard and RT flush
3054 - iris: Disable a PIPE_CONTROL workaround on Icelake
3117 - iris: PIPE_CONTROL workarounds for GPGPU mode
3310 - i965: Use genxml for emitting PIPE_CONTROL.
3311 - i965: Reimplement all the PIPE_CONTROL rules.
H A D20.0.0.rst1635 - anv: Use PIPE_CONTROL flushes to implement the gen8 VF cache WA
2140 - genxml: add new Gen11+ PIPE_CONTROL field
2141 - iris: handle new PIPE_CONTROL field
H A D20.2.0.rst2183 - iris: Update cache coherency matrix on PIPE_CONTROL.
2191 - iris: Emit single render target flush PIPE_CONTROL on format mismatch.
3083 - intel/genxml: add PIPE_CONTROL command cache invalidate bit
H A D20.1.0.rst2358 - anv: Use the PIPE_CONTROL instead of bits for the CS stall W/A
H A D21.1.0.rst3160 - genxml: Add PIPE_CONTROL protected memory bits
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A DgenX_pipe_control.c71 * Emit a series of PIPE_CONTROL commands, taking into account any
76 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
77 * Restrictions for PIPE_CONTROL.
91 /* Recursive PIPE_CONTROL workarounds --------------------------------
100 * "[Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush
101 * Enable = 1, a PIPE_CONTROL with any non-zero post-sync-op is
108 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
114 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
116 * needs to be sent prior to the PIPE_CONTROL wit
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/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A DgenX_pipe_control.c71 * Emit a series of PIPE_CONTROL commands, taking into account any
76 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
77 * Restrictions for PIPE_CONTROL.
91 /* Recursive PIPE_CONTROL workarounds --------------------------------
100 * "[Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush
101 * Enable = 1, a PIPE_CONTROL with any non-zero post-sync-op is
108 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
114 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields
116 * needs to be sent prior to the PIPE_CONTROL wit
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/xsrc/external/mit/MesaLib/dist/src/intel/blorp/
H A Dblorp_genX_exec.h240 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall
243 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL
246 blorp_emit(batch, GENX(PIPE_CONTROL), pc) {
1353 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
1612 blorp_emit(batch, GENX(PIPE_CONTROL), pipe) {
1731 blorp_emit(batch, GENX(PIPE_CONTROL), pc) {
1839 /* PIPE_CONTROL w/ all bits clear except for “Post-Sync Operation” must set
1842 blorp_emit(batch, GENX(PIPE_CONTROL), pc) {
1858 blorp_emit(batch, GENX(PIPE_CONTROL), pipe) {
1892 blorp_emit(batch, GENX(PIPE_CONTROL), pip
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/xsrc/external/mit/MesaLib.old/dist/src/intel/blorp/
H A Dblorp_genX_exec.h1271 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL
1515 blorp_emit(batch, GENX(PIPE_CONTROL), pipe) {
1719 /* PIPE_CONTROL w/ all bits clear except for “Post-Sync Operation” must set
1722 blorp_emit(batch, GENX(PIPE_CONTROL), pc) {
1738 blorp_emit(batch, GENX(PIPE_CONTROL), pipe) {
1768 blorp_emit(batch, GENX(PIPE_CONTROL), pipe) {
/xsrc/external/mit/MesaLib/dist/src/intel/common/
H A Dmi_builder.h1173 mi_builder_emit(b, GENX(PIPE_CONTROL), pc) {
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/iris/
H A Diris_state.c535 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
2546 /* The PIPE_CONTROL command description says:
5460 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
5936 * Emit a series of PIPE_CONTROL commands, taking into account any
5941 * Synchronization of the 3D Pipeline > PIPE_CONTROL Command > Programming
5942 * Restrictions for PIPE_CONTROL.
5956 /* Recursive PIPE_CONTROL workarounds --------------------------------
5963 /* The PIPE_CONTROL "VF Cache Invalidation Enable" bit description
5969 * PIPE_CONTROL,
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/iris/
H A Diris_state.c415 * Software must program PIPE_CONTROL command
447 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
448 * which, according the PIPE_CONTROL instruction documentation in the
456 * invalidation through a PIPE_CONTROL does nothing whatsoever in
650 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
1669 /* According to the Broadwell PIPE_CONTROL documentation, software should
1670 * emit a PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set
1689 /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
5897 /* The PIPE_CONTROL comman
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/crocus/
H A Dcrocus_state.c459 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
460 * which, according the PIPE_CONTROL instruction documentation in the
468 * invalidation through a PIPE_CONTROL does nothing whatsoever in
1079 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1085 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1087 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1206 * Emit a PIPE_CONTROL command for gen7 with the CS Stall bit set.
1244 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
1270 * MI_FLUSH or PIPE_CONTROL prio
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