Searched refs:WRITE_VIP32 (Results 1 - 11 of 11) sorted by relevance

/xsrc/external/mit/xf86-video-geode/dist/src/cim/
H A Dcim_vip.c132 WRITE_VIP32(VIP_CONTROL1, vip_control1);
133 WRITE_VIP32(VIP_CONTROL2, vip_control2);
134 WRITE_VIP32(VIP_CONTROL3, vip_control3);
173 WRITE_VIP32(VIP_CONTROL3, vip_control3);
174 WRITE_VIP32(VIP_601_HORZ_START, buffer->horz_start);
175 WRITE_VIP32(VIP_601_VBI_START, buffer->vbi_start);
176 WRITE_VIP32(VIP_601_VBI_END, buffer->vbi_start + buffer->vbi_height - 1);
177 WRITE_VIP32(VIP_601_EVEN_START_STOP,
180 WRITE_VIP32(VIP_601_ODD_START_STOP,
183 WRITE_VIP32(VIP_ODD_FIELD_DETEC
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H A Dcim_vop.c269 WRITE_VIP32(VIP_CONTROL2, control2);
H A Dcim_defs.h73 #define WRITE_VIP32(offset, value) \ macro
H A Dcim_vg.c677 WRITE_VIP32(VIP_CONTROL1, 0);
678 WRITE_VIP32(VIP_CONTROL2, 0);
679 WRITE_VIP32(VIP_INTERRUPT, VIP_ALL_INTERRUPTS | (VIP_ALL_INTERRUPTS >> 16));
/xsrc/external/mit/xf86-video-nsc/dist/src/gfx/
H A Dvip_1400.c47 WRITE_VIP32(SC1400_VIP_CONFIG, 0x30012);
53 WRITE_VIP32(SC1400_VIP_CONTROL, value);
74 WRITE_VIP32(SC1400_VIP_EVEN_BASE, even | 0x00800000);
75 WRITE_VIP32(SC1400_VIP_ODD_BASE, odd | 0x00800000);
93 WRITE_VIP32(SC1400_VIP_PITCH, pitch & 0x0000FFFC);
118 WRITE_VIP32(SC1400_VIP_CONTROL, value);
138 WRITE_VIP32(SC1400_VBI_EVEN_BASE, even | 0x00800000);
139 WRITE_VIP32(SC1400_VBI_ODD_BASE, odd | 0x00800000);
157 WRITE_VIP32(SC1400_VBI_PITCH, pitch & 0x0000FFFC);
H A Dvip_1200.c184 WRITE_VIP32(SC1200_VIP_CONTROL, value);
219 WRITE_VIP32(SC1200_VIP_CONTROL, value);
241 WRITE_VIP32(SC1200_VIP_EVEN_BASE, even + (unsigned long)gfx_phys_fbptr);
243 WRITE_VIP32(SC1200_VIP_ODD_BASE, odd + (unsigned long)gfx_phys_fbptr);
261 WRITE_VIP32(SC1200_VIP_PITCH, pitch & SC1200_VIP_PITCH_MASK);
285 WRITE_VIP32(SC1200_VIP_CONFIG, config | SC1200_VIP_MODE_C);
314 WRITE_VIP32(SC1200_VIP_CONTROL, value);
346 WRITE_VIP32(SC1200_VIP_CONFIG, config);
369 WRITE_VIP32(SC1200_VBI_EVEN_BASE, even & ~0xf);
371 WRITE_VIP32(SC1200_VBI_ODD_BAS
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H A Dgfx_defs.h196 #define WRITE_VIP32(offset, value) \ macro
/xsrc/external/mit/xf86-video-geode/dist/src/gfx/
H A Dvip_1200.c52 WRITE_VIP32(SC1200_VIP_CONTROL, value);
87 WRITE_VIP32(SC1200_VIP_CONTROL, value);
109 WRITE_VIP32(SC1200_VIP_EVEN_BASE,
112 WRITE_VIP32(SC1200_VIP_ODD_BASE, odd + (unsigned long) gfx_phys_fbptr);
130 WRITE_VIP32(SC1200_VIP_PITCH, pitch & SC1200_VIP_PITCH_MASK);
154 WRITE_VIP32(SC1200_VIP_CONFIG, config | SC1200_VIP_MODE_C);
183 WRITE_VIP32(SC1200_VIP_CONTROL, value);
215 WRITE_VIP32(SC1200_VIP_CONFIG, config);
238 WRITE_VIP32(SC1200_VBI_EVEN_BASE, even & ~0xf);
240 WRITE_VIP32(SC1200_VBI_ODD_BAS
[all...]
H A Dgfx_defs.h92 #define WRITE_VIP32(offset, value) \ macro
/xsrc/external/mit/xf86-video-nsc/dist/src/
H A Dnsc_regacc.c229 WRITE_VIP32(offset, value);
/xsrc/external/mit/xf86-video-geode/dist/src/
H A Dgx_regacc.c142 WRITE_VIP32(offset, value);

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