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    Searched refs:PIPE_CONTROL_RENDER_TARGET_FLUSH (Results 1 - 25 of 51) sorted by relevancy

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  /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
brw_pipe_control.h 54 PIPE_CONTROL_RENDER_TARGET_FLUSH = (1 << 13),
70 PIPE_CONTROL_RENDER_TARGET_FLUSH)
genX_pipe_control.c 97 if (GFX_VER == 6 && (flags & PIPE_CONTROL_RENDER_TARGET_FLUSH)) {
162 assert(!(flags & (PIPE_CONTROL_RENDER_TARGET_FLUSH |
190 if (flags & (PIPE_CONTROL_RENDER_TARGET_FLUSH |
218 PIPE_CONTROL_RENDER_TARGET_FLUSH)));
363 PIPE_CONTROL_RENDER_TARGET_FLUSH |
451 const uint32_t wa_bits = PIPE_CONTROL_RENDER_TARGET_FLUSH |
483 flags & PIPE_CONTROL_RENDER_TARGET_FLUSH;
491 pc.WriteCacheFlush = flags & PIPE_CONTROL_RENDER_TARGET_FLUSH;
gfx8_depth_state.c 149 brw->stencil_write_enabled ? PIPE_CONTROL_RENDER_TARGET_FLUSH : 0;
brw_pipe_control.c 361 int flags = PIPE_CONTROL_RENDER_TARGET_FLUSH;
brw_program.c 370 PIPE_CONTROL_RENDER_TARGET_FLUSH);
374 PIPE_CONTROL_RENDER_TARGET_FLUSH);
380 bits |= PIPE_CONTROL_RENDER_TARGET_FLUSH;
394 PIPE_CONTROL_RENDER_TARGET_FLUSH |
400 PIPE_CONTROL_RENDER_TARGET_FLUSH);
brw_misc_state.c 531 PIPE_CONTROL_RENDER_TARGET_FLUSH |
782 PIPE_CONTROL_RENDER_TARGET_FLUSH |
  /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
brw_pipe_control.h 54 PIPE_CONTROL_RENDER_TARGET_FLUSH = (1 << 13),
70 PIPE_CONTROL_RENDER_TARGET_FLUSH)
genX_pipe_control.c 97 if (GEN_GEN == 6 && (flags & PIPE_CONTROL_RENDER_TARGET_FLUSH)) {
160 assert(!(flags & (PIPE_CONTROL_RENDER_TARGET_FLUSH |
188 if (flags & (PIPE_CONTROL_RENDER_TARGET_FLUSH |
216 PIPE_CONTROL_RENDER_TARGET_FLUSH)));
359 PIPE_CONTROL_RENDER_TARGET_FLUSH |
447 const uint32_t wa_bits = PIPE_CONTROL_RENDER_TARGET_FLUSH |
479 flags & PIPE_CONTROL_RENDER_TARGET_FLUSH;
487 pc.WriteCacheFlush = flags & PIPE_CONTROL_RENDER_TARGET_FLUSH;
gen8_depth_state.c 149 brw->stencil_write_enabled ? PIPE_CONTROL_RENDER_TARGET_FLUSH : 0;
brw_pipe_control.c 357 int flags = PIPE_CONTROL_RENDER_TARGET_FLUSH;
brw_program.c 331 PIPE_CONTROL_RENDER_TARGET_FLUSH);
335 PIPE_CONTROL_RENDER_TARGET_FLUSH);
341 bits |= PIPE_CONTROL_RENDER_TARGET_FLUSH;
355 PIPE_CONTROL_RENDER_TARGET_FLUSH |
361 PIPE_CONTROL_RENDER_TARGET_FLUSH);
brw_misc_state.c 532 PIPE_CONTROL_RENDER_TARGET_FLUSH |
693 PIPE_CONTROL_RENDER_TARGET_FLUSH |
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/crocus/
crocus_pipe_control.c 214 int flags = PIPE_CONTROL_RENDER_TARGET_FLUSH;
287 PIPE_CONTROL_RENDER_TARGET_FLUSH |
313 PIPE_CONTROL_RENDER_TARGET_FLUSH |
353 PIPE_CONTROL_RENDER_TARGET_FLUSH;
360 bits |= PIPE_CONTROL_RENDER_TARGET_FLUSH;
crocus_fine_fence.c 74 PIPE_CONTROL_RENDER_TARGET_FLUSH |
crocus_resolve.c 422 PIPE_CONTROL_RENDER_TARGET_FLUSH |
553 PIPE_CONTROL_RENDER_TARGET_FLUSH);
564 PIPE_CONTROL_RENDER_TARGET_FLUSH);
668 PIPE_CONTROL_RENDER_TARGET_FLUSH |
crocus_context.h 247 PIPE_CONTROL_RENDER_TARGET_FLUSH = (1 << 13),
265 PIPE_CONTROL_RENDER_TARGET_FLUSH)
  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/iris/
iris_pipe_control.c 191 [IRIS_DOMAIN_RENDER_WRITE] = PIPE_CONTROL_RENDER_TARGET_FLUSH,
199 [IRIS_DOMAIN_RENDER_WRITE] = PIPE_CONTROL_RENDER_TARGET_FLUSH,
298 PIPE_CONTROL_RENDER_TARGET_FLUSH |
319 PIPE_CONTROL_RENDER_TARGET_FLUSH |
356 PIPE_CONTROL_RENDER_TARGET_FLUSH |
iris_fine_fence.c 68 PIPE_CONTROL_RENDER_TARGET_FLUSH |
iris_blit.c 544 PIPE_CONTROL_RENDER_TARGET_FLUSH,
748 PIPE_CONTROL_RENDER_TARGET_FLUSH,
iris_context.h 327 PIPE_CONTROL_RENDER_TARGET_FLUSH = (1 << 13),
347 PIPE_CONTROL_RENDER_TARGET_FLUSH)
iris_blorp.c 283 PIPE_CONTROL_RENDER_TARGET_FLUSH |
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/iris/
iris_pipe_control.c 160 PIPE_CONTROL_RENDER_TARGET_FLUSH |
193 PIPE_CONTROL_RENDER_TARGET_FLUSH;
iris_clear.c 255 iris_emit_end_of_pipe_sync(batch, PIPE_CONTROL_RENDER_TARGET_FLUSH);
280 iris_emit_end_of_pipe_sync(batch, PIPE_CONTROL_RENDER_TARGET_FLUSH);
iris_context.h 205 PIPE_CONTROL_RENDER_TARGET_FLUSH = (1 << 13),
222 PIPE_CONTROL_RENDER_TARGET_FLUSH)
iris_blorp.c 279 PIPE_CONTROL_RENDER_TARGET_FLUSH |

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