| /src/sys/dev/ic/ |
| arn5416.c | 188 AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);
218 AR_WRITE(sc, AR_PHY(0x37), phy);
235 AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon);
244 AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset,
252 AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg);
263 AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
271 AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
276 AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
280 AR_WRITE(sc, AR_PHY_SETTLING, reg);
285 AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg)
[all...] |
| athn.c | 495 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff);
496 AR_WRITE(sc, AR_BSSMSKU, 0xffff);
501 AR_WRITE(sc, AR_MCAST_FIL0, 0xffffffff);
502 AR_WRITE(sc, AR_MCAST_FIL1, 0xffffffff);
504 AR_WRITE(sc, AR_FILT_OFDM, 0);
505 AR_WRITE(sc, AR_FILT_CCK, 0);
506 AR_WRITE(sc, AR_MIBC, 0);
507 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
508 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
511 AR_WRITE(sc, AR_PHY_ERR_1, 0)
[all...] |
| arn9280.c | 180 AR_WRITE(sc, AR_PHY(637), 0x00000000);
181 AR_WRITE(sc, AR_PHY(638), 0xefff0301);
182 AR_WRITE(sc, AR_PHY(639), 0xca9228ee);
185 AR_WRITE(sc, AR_PHY(637), 0x00fffeff);
186 AR_WRITE(sc, AR_PHY(638), 0x00f5f9ff);
187 AR_WRITE(sc, AR_PHY(639), 0xb79f6427);
196 AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);
222 AR_WRITE(sc, AR_AN_SYNTH9, reg);
227 AR_WRITE(sc, AR9280_PHY_SYNTH_CONTROL, phy);
245 AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon)
[all...] |
| arn9285.c | 191 AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon);
192 AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0, modal->antCtrlChain);
197 AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0, reg);
209 AR_WRITE(sc, AR_PHY_GAIN_2GHZ, reg);
221 AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
230 AR_WRITE(sc, AR_PHY_RXGAIN, reg);
236 AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
252 AR_WRITE(sc, AR_PHY_MULTICHAIN_GAIN_CTL, reg);
260 AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);
318 AR_WRITE(sc, AR9285_AN_RF2G3, reg)
[all...] |
| arn9380.c | 275 AR_WRITE(sc, AR_PHY_SYNTH_CONTROL, AR9380_BMODE);
280 AR_WRITE(sc, AR_PHY_SYNTH_CONTROL, 0);
291 AR_WRITE(sc, AR_PHY_65NM_CH0_SYNTH7, phy);
294 AR_WRITE(sc, AR_PHY_65NM_CH0_SYNTH7, phy | AR9380_LOAD_SYNTH);
319 AR_WRITE(sc, AR9485_PHY_65NM_CH0_TOP2, reg);
325 AR_WRITE(sc, AR_PHY_65NM_CH0_TOP, reg);
330 AR_WRITE(sc, AR_PHY_65NM_CH0_THERM, reg);
336 AR_WRITE(sc, AR_PHY_SWITCH_COM, reg);
339 AR_WRITE(sc, AR_PHY_SWITCH_COM_2, reg);
345 AR_WRITE(sc, AR_PHY_SWITCH_CHAIN(i), reg)
[all...] |
| arn9287.c | 167 AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon);
172 AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset,
180 AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg);
187 AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
194 AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
204 AR_WRITE(sc, AR_PHY_SETTLING, reg);
208 AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
214 AR_WRITE(sc, AR_PHY_RF_CTL4, reg);
218 AR_WRITE(sc, AR_PHY_RF_CTL3, reg);
222 AR_WRITE(sc, AR_PHY_CCA(0), reg)
[all...] |
| arn5008.c | 390 AR_WRITE(sc, AR7010_GPIO_OUT, reg);
398 AR_WRITE(sc, AR_GPIO_IN_OUT, reg);
416 AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
441 AR_WRITE(sc, AR_GPIO_OUTPUT_MUX(mux), reg);
446 AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
459 AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg);
718 AR_WRITE(sc, AR_RXDP, SIMPLEQ_FIRST(&rxq->head)->bf_daddr);
719 AR_WRITE(sc, AR_CR, AR_CR_RXE);
822 AR_WRITE(sc, AR_RXDP, nbf->bf_daddr);
949 AR_WRITE(sc, AR_RXDP, bf->bf_daddr)
[all...] |
| arn9003.c | 543 AR_WRITE(sc, AR_GPIO_IN_OUT, reg);
555 AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
571 AR_WRITE(sc, AR_GPIO_OUTPUT_MUX(mux), reg);
576 AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
589 AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg);
827 AR_WRITE(sc, AR_Q_STATUS_RING_START,
829 AR_WRITE(sc, AR_Q_STATUS_RING_END,
846 AR_WRITE(sc, AR_RXBP_THRESH, reg);
849 AR_WRITE(sc, AR_DATABUF_SIZE, ATHN_RXBUFSZ - sizeof(*ds));
862 AR_WRITE(sc, AR_LP_RXDP, bf->bf_daddr)
[all...] |
| athnreg.h | 1462 #define AR_WRITE(sc, reg, val) \
1469 AR_WRITE(sc, reg, AR_READ(sc, reg) | (mask))
1472 AR_WRITE(sc, reg, AR_READ(sc, reg) & ~(mask))
|
| /src/sys/dev/usb/ |
| if_athn_usb.c | 1508 AR_WRITE(sc, AR_RX_FILTER, reg);
1733 AR_WRITE(sc, AR_CR, AR_CR_RXE);
|
