| /src/sys/dev/pcmcia/ |
| if_wi_pcmcia.c | 449 CSR_WRITE_2(sc, WI_PARAM0, WI_AUX_KEY0);
450 CSR_WRITE_2(sc, WI_PARAM1, WI_AUX_KEY1);
451 CSR_WRITE_2(sc, WI_PARAM2, WI_AUX_KEY2);
452 CSR_WRITE_2(sc, WI_CNTL, WI_CNTL_AUX_ENA_CNTL);
456 CSR_WRITE_2(sc, WI_PARAM0, 0);
457 CSR_WRITE_2(sc, WI_PARAM1, 0);
458 CSR_WRITE_2(sc, WI_PARAM2, 0);
459 CSR_WRITE_2(sc, WI_COMMAND, WI_CMD_READEE);
465 CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_CMD);
467 CSR_WRITE_2(sc, WI_AUX_PAGE, WI_SBCF_PDIADDR / WI_AUX_PGSZ)
[all...] |
| /src/sys/arch/sandpoint/stand/altboot/ |
| fxp.c | 91 #define CSR_WRITE_2(l, r, v) out16rb((l)->iobase+(r), (v))
418 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
420 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
423 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
433 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
444 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
446 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
453 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
456 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
470 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS)
[all...] |
| skg.c | 48 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v))
221 CSR_WRITE_2(l, SK_CSR, CSR_SW_RESET);
222 CSR_WRITE_2(l, SK_CSR, CSR_MASTER_RESET);
223 CSR_WRITE_2(l, SK_LINK_CTRL, LINK_RESET_SET);
225 CSR_WRITE_2(l, SK_CSR, CSR_SW_UNRESET);
227 CSR_WRITE_2(l, SK_CSR, CSR_MASTER_UNRESET);
228 CSR_WRITE_2(l, SK_LINK_CTRL, LINK_RESET_CLEAR);
247 CSR_WRITE_2(l, YUKON_SA1 + i * 4,
323 CSR_WRITE_2(l, YUKON_GPCR, reg);
403 CSR_WRITE_2(l, YUKON_SMICR, SMICR_PHYAD(phy) | SMICR_REGAD(reg)
[all...] |
| stg.c | 43 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v))
192 CSR_WRITE_2(l, STGE_EepromCtrl,
231 CSR_WRITE_2(l, STGE_IntEnable, 0);
232 CSR_WRITE_2(l, STGE_ReceiveMode, RM_ReceiveUnicast |
238 CSR_WRITE_2(l, STGE_MaxFrameSize, FRAMESIZE);
244 CSR_WRITE_2(l, STGE_DebugCtrl,
246 CSR_WRITE_2(l, STGE_DebugCtrl,
248 CSR_WRITE_2(l, STGE_DebugCtrl,
|
| vge.c | 49 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v))
294 CSR_WRITE_2(l, VR_RDCSIZE, NRXDESC - 1);
295 CSR_WRITE_2(l, VR_RBRDU, NRXDESC - 1);
297 CSR_WRITE_2(l, VR_TDCSIZE, 0);
302 CSR_WRITE_2(l, VR_TDCSR, 01);
330 CSR_WRITE_2(l, VR_TDCSR, 04);
448 CSR_WRITE_2(l, VR_MIIDATA, data);
|
| kse.c | 50 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v))
151 CSR_WRITE_2(l, CIDR, 1);
264 CSR_WRITE_2(l, P1CR4, val);
|
| nvt.c | 49 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v))
232 CSR_WRITE_2(l, VR_ISR, ~0);
233 CSR_WRITE_2(l, VR_IEN, 0);
366 CSR_WRITE_2(l, VR_MIIDATA, data);
|
| rge.c | 49 #define CSR_WRITE_2(l, r, v) out16rb((l)->csr+(r), (v))
220 CSR_WRITE_2(l, RGE_RMS, FRAMESIZE);
227 CSR_WRITE_2(l, RGE_ISR, ~0);
228 CSR_WRITE_2(l, RGE_IMR, 0);
|
| /src/sys/dev/pci/ |
| if_vte.c | 343 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ |
366 CSR_WRITE_2(sc, VTE_MMWD, val);
367 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE |
419 CSR_WRITE_2(sc, VTE_MRICR, val);
427 CSR_WRITE_2(sc, VTE_MTICR, val);
814 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START);
890 CSR_WRITE_2(sc, VTE_MCR0, mcr);
976 CSR_WRITE_2(sc, VTE_MIER, 0);
996 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);
1181 CSR_WRITE_2(sc, VTE_MRDCR, prog
[all...] |
| if_vtevar.h | 154 #define CSR_WRITE_2(_sc, reg, val) \
|
| if_stge.c | 225 #define CSR_WRITE_2(_sc, reg, val) \
1161 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
1597 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
1604 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
1625 CSR_WRITE_2(sc, STGE_IntStatus, 0xffff);
1626 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
1640 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16);
1641 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16);
1646 CSR_WRITE_2(sc, STGE_MaxFrameSize,
1667 CSR_WRITE_2(sc, STGE_DebugCtrl
[all...] |
| if_ipwreg.h | 325 #define CSR_WRITE_2(sc, reg, val) \
345 CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \
|
| if_kse.c | 71 #define CSR_WRITE_2(sc, off, val) \
451 CSR_WRITE_2(sc, SIDER, 1);
802 CSR_WRITE_2(sc, SGCR3, i | CR3_USEFC);
878 CSR_WRITE_2(sc, GRR, 1);
880 CSR_WRITE_2(sc, GRR, 0);
883 CSR_WRITE_2(sc, SIDER, 1);
1356 CSR_WRITE_2(sc, P1CR4, p1cr4);
1436 CSR_WRITE_2(sc, phy1csr[reg], val);
1509 CSR_WRITE_2(sc, IACR, reg);
1525 CSR_WRITE_2(sc, IACR, EVCNTBR + 0x100 + p)
[all...] |
| if_vge.c | 262 #define CSR_WRITE_2(sc, reg, val) \
277 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (x))
284 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(x))
521 CSR_WRITE_2(sc, VGE_MIIDATA, val);
1358 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim);
1715 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0);
1806 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_NTXDESC - 1);
1809 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_NRXDESC - 1);
1810 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_NRXDESC);
1817 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0)
[all...] |
| if_wi_pci.c | 302 CSR_WRITE_2(sc, WI_INT_EN, 0);
303 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
|
| if_vr.c | 288 #define CSR_WRITE_2(sc, reg, val) \
337 CSR_WRITE_2(sc, reg, \
341 CSR_WRITE_2(sc, reg, \
926 CSR_WRITE_2(sc, VR_IMR, 0x0000);
931 CSR_WRITE_2(sc, VR_ISR, status);
989 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1266 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL | VR_CMD_START |
1271 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
1272 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1402 CSR_WRITE_2(sc, VR_IMR, 0x0000)
[all...] |
| /src/sys/dev/ic/ |
| an.c | 461 CSR_WRITE_2(sc, AN_INT_EN, 0);
462 CSR_WRITE_2(sc, AN_EVENT_ACK, ~0);
467 CSR_WRITE_2(sc, AN_INT_EN, 0);
486 CSR_WRITE_2(sc, AN_EVENT_ACK, ~0);
501 CSR_WRITE_2(sc, AN_EVENT_ACK, status & ~(AN_INTRS));
526 CSR_WRITE_2(sc, AN_INT_EN, AN_INTRS);
550 CSR_WRITE_2(sc, AN_SW0, AN_MAGIC);
678 CSR_WRITE_2(sc, AN_INT_EN, AN_INTRS);
697 CSR_WRITE_2(sc, AN_INT_EN, 0);
1388 CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX)
[all...] |
| i82557.c | 613 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
615 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
618 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
655 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
666 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
668 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL,
675 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
678 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0);
703 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
716 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL
[all...] |
| anvar.h | 50 #define CSR_WRITE_2(sc, reg, val) \
|
| wivar.h | 233 #define CSR_WRITE_2(sc, reg, val) \
255 #define CSR_WRITE_2(sc, reg, val) \
|
| rtl81x9.c | 295 CSR_WRITE_2(sc, RTK_MII, 0);
497 CSR_WRITE_2(sc, rtk8139_reg, val);
970 CSR_WRITE_2(sc, RTK_COMMAND, RTK_CMD_TX_ENB);
971 CSR_WRITE_2(sc, RTK_COMMAND,
1078 CSR_WRITE_2(sc, RTK_CURRXADDR, (new_rx - 16) % RTK_RXBUFLEN);
1178 CSR_WRITE_2(sc, RTK_IMR, 0x0000);
1189 CSR_WRITE_2(sc, RTK_ISR, status);
1214 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS);
1409 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS);
1491 CSR_WRITE_2(sc, RTK_IMR, 0x0000)
[all...] |
| bwi.c | 813 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
1261 CSR_WRITE_2(sc, data_reg, v);
1274 CSR_WRITE_2(sc, BWI_MOBJ_DATA_UNALIGN, v >> 16);
1277 CSR_WRITE_2(sc, BWI_MOBJ_DATA, v & 0xffff);
1321 CSR_WRITE_2(mac->mac_sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC);
1402 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);
1419 CSR_WRITE_2(sc, 0x60e, 0);
1420 CSR_WRITE_2(sc, 0x610, 0x8000);
1421 CSR_WRITE_2(sc, 0x604, 0);
1422 CSR_WRITE_2(sc, 0x606, 0x200)
[all...] |
| rtl8169.c | 408 CSR_WRITE_2(sc, re8139_reg, val);
514 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF);
1554 CSR_WRITE_2(sc, RTK_ISR, status);
1898 CSR_WRITE_2(sc, RTK_CPLUS_CMD, cfg);
1903 CSR_WRITE_2(sc, RTK_IM, 0x0000);
1905 CSR_WRITE_2(sc, RTK_IM, 0x5151);
2010 CSR_WRITE_2(sc, RTK_IMR, 0);
2012 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_IM_HW);
2014 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS);
2079 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383)
[all...] |
| wi.c | 388 CSR_WRITE_2(sc, WI_INT_EN, 0);
389 CSR_WRITE_2(sc, WI_EVENT_ACK, ~0);
645 CSR_WRITE_2(sc, WI_INT_EN, 0);
646 CSR_WRITE_2(sc, WI_EVENT_ACK, ~0);
653 CSR_WRITE_2(sc, WI_INT_EN, 0);
663 CSR_WRITE_2(sc, WI_INT_EN, WI_INTRS);
685 CSR_WRITE_2(sc, WI_EVENT_ACK, ~0);
718 CSR_WRITE_2(sc, WI_EVENT_ACK, sc->sc_status);
740 CSR_WRITE_2(sc, WI_INT_EN, WI_INTRS);
960 CSR_WRITE_2(sc, WI_INT_EN, WI_INTRS)
[all...] |
| /src/sys/arch/evbarm/ixm1200/ |
| nappi_nppb.c | 67 #define CSR_WRITE_2(sc, reg, val) \
|
