| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_gfx_v8_0.c | 861 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
903 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
1262 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1265 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1273 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
1284 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1290 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1293 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
1576 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1);
1582 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2)
[all...] |
| amdgpu_gfx_v10_0.c | 270 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
289 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
315 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
342 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
360 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
428 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
441 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
482 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
529 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
962 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0))
[all...] |
| amdgpu_gfx_v7_0.c | 2112 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2159 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2172 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2176 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2198 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2210 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2239 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
2276 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2281 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
2283 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2)
[all...] |
| nvd.h | 50 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
54 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
|
| si_enums.h | 171 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
174 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
|
| soc15d.h | 52 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
56 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
|
| amdgpu_gfx_v6_0.c | 1812 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1834 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
1845 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1848 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1857 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1877 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1882 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1884 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1926 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2041 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5))
[all...] |
| amdgpu_gfx_v9_0.c | 755 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
778 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
808 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
835 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
854 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
948 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
962 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
996 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
1038 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
1640 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0))
[all...] |
| vid.h | 109 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
113 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
|
| cikd.h | 227 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
231 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
|
| amdgpu_amdkfd_gfx_v10.c | 371 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
|
| amdgpu_amdkfd_gfx_v9.c | 359 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
|
| sid.h | 1660 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
1664 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_ni.c | 1418 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1424 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1440 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1445 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1451 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1461 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1567 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1585 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1591 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1595 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0))
[all...] |
| radeon_si.c | 3388 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3391 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3400 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3419 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3422 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3427 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3433 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3440 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3454 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3457 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3))
[all...] |
| radeon_cik.c | 3491 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3547 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3576 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3588 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3615 radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
3646 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
3652 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3707 radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
3754 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3757 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2)
[all...] |
| radeon_r600.c | 2729 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2874 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2912 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2918 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2926 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
2931 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
2934 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2938 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2969 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2976 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0))
[all...] |
| r300d.h | 47 /* PACKET3 op code */
66 #define PACKET3(op, n) (CP_PACKET3 | \
|
| cikd.h | 1693 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
1697 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
|
| sid.h | 1597 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
1601 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
|
| radeon_evergreen.c | 2941 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
2946 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2952 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
2959 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
3013 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
3032 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3038 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3042 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
|
| rv515d.h | 190 /* PACKET3 op code */
206 #define PACKET3(op, n) (CP_PACKET3 | \
|
| rv770d.h | 990 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
|
| nid.h | 1159 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
|
| r100d.h | 47 /* PACKET3 op code */
65 #define PACKET3(op, n) (CP_PACKET3 | \
|
