| /src/sys/arch/riscv/starfive/ |
| jh7110_trng.c | 62 #define RD4(sc, reg) \
144 #define RD4(sc, reg) \
173 const uint32_t stat = RD4(sc, JH7110_TRNG_STAT);
181 data[0] = RD4(sc, JH7110_TRNG_DATA0);
182 data[1] = RD4(sc, JH7110_TRNG_DATA1);
183 data[2] = RD4(sc, JH7110_TRNG_DATA2);
184 data[3] = RD4(sc, JH7110_TRNG_DATA3);
185 data[4] = RD4(sc, JH7110_TRNG_DATA4);
186 data[5] = RD4(sc, JH7110_TRNG_DATA5);
187 data[6] = RD4(sc, JH7110_TRNG_DATA6)
[all...] |
| jh7110_syscon.c | 52 #define RD4(sc, reg) \
81 return RD4(sc, reg);
|
| /src/sys/dev/ic/ |
| cdnsiic.c | 88 #define RD4(sc, reg) \
148 sr_val = RD4(sc, SR_REG);
149 isr_val = RD4(sc, ISR_REG);
169 val = RD4(sc, ISR_REG);
192 val = RD4(sc, CR_REG);
196 WR4(sc, ISR_REG, RD4(sc, ISR_REG));
199 fifo_space = FIFO_DEPTH - RD4(sc, TRANS_SIZE_REG);
229 val = RD4(sc, CR_REG);
232 WR4(sc, ISR_REG, RD4(sc, ISR_REG));
241 *data = RD4(sc, DATA_REG) & 0xff
[all...] |
| bcmgenet.c | 87 #define RD4(sc, reg) \
103 if ((RD4(sc, GENET_MDIO_CMD) & GENET_MDIO_START_BUSY) == 0) {
104 *val = RD4(sc, GENET_MDIO_CMD) & 0xffff;
130 if ((RD4(sc, GENET_MDIO_CMD) & GENET_MDIO_START_BUSY) == 0)
159 val = RD4(sc, GENET_EXT_RGMII_OOB_CTRL);
169 val = RD4(sc, GENET_UMAC_CMD);
351 cmd = RD4(sc, GENET_UMAC_CMD);
395 val = RD4(sc, GENET_SYS_RBUF_FLUSH_CTRL);
419 val = RD4(sc, GENET_RBUF_CTRL);
448 val = RD4(sc, GENET_RX_DMA_RING_TIMEOUT(qid))
[all...] |
| dwc_eqos.c | 115 #define RD4(sc, reg) \
145 addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS);
147 *val = RD4(sc, GMAC_MAC_MDIO_DATA) & 0xFFFF;
179 addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS);
203 conf = RD4(sc, GMAC_MAC_CONFIGURATION);
491 pfil = RD4(sc, GMAC_MAC_PACKET_FILTER);
559 val = RD4(sc, GMAC_DMA_MODE);
623 val = RD4(sc, GMAC_DMA_CHAN0_CONTROL);
628 val = RD4(sc, GMAC_DMA_CHAN0_TX_CONTROL);
634 val = RD4(sc, GMAC_DMA_CHAN0_RX_CONTROL)
[all...] |
| /src/sys/arch/arm/ti/ |
| ti_rng.c | 64 #define RD4(sc, reg) \
103 if ((RD4(sc, TRNG_CONTROL_REG) & TRNG_CONTROL_ENABLE) == 0) {
129 if (RD4(sc, TRNG_STATUS_REG) & TRNG_STATUS_READY)
135 buf[0] = RD4(sc, TRNG_OUTPUT_L_REG);
136 buf[1] = RD4(sc, TRNG_OUTPUT_H_REG);
|
| ti_gpio.c | 139 #define RD4(sc, reg) \
157 oe = RD4(sc, GPIO_OE);
229 data = RD4(sc, GPIO_DATAOUT);
231 data = RD4(sc, GPIO_DATAIN);
273 val = RD4(sc, GPIO_IRQENABLE1);
322 val = RD4(sc, GPIO_LEVELDETECT0);
329 val = RD4(sc, GPIO_LEVELDETECT1);
336 val = RD4(sc, GPIO_RISINGDETECT);
343 val = RD4(sc, GPIO_FALLINGDETECT);
352 val = RD4(sc, GPIO_IRQENABLE1)
[all...] |
| ti_usbtll.c | 97 #define RD4(sc, reg) \
117 val = RD4(sc, USBTLL_CHANNEL_CONF(port));
133 val = RD4(sc, USBTLL_SYSSTATUS);
155 val = RD4(sc, USBTLL_SHARED_CONF);
|
| ti_dpll_clock.c | 133 #define RD4(sc, space) \
231 val = RD4(sc, REG_MULT_DIV1);
269 control = RD4(sc, REG_CONTROL);
274 while (RD4(sc, REG_IDLEST) != AM3_ST_MN_BYPASS)
285 while (RD4(sc, REG_IDLEST) != AM3_ST_DPLL_CLK)
309 control = RD4(sc, REG_CONTROL);
324 while ((RD4(sc, REG_IDLEST) & OMAP3_ST_MPU_CLK) != 0)
341 val = RD4(sc, REG_MULT_DIV1);
|
| ti_wdt.c | 88 #define RD4(sc, reg) \
100 val = RD4(sc, WDT_WWPS);
121 val = RD4(sc, WDT_WDSC);
125 val = RD4(sc, WDT_WDSC);
194 val = RD4(sc, WDT_WTGR);
|
| ti_usb.c | 123 #define RD4(sc, reg) \
134 val = RD4(sc, UHH_SYSCONFIG);
143 val = RD4(sc, UHH_SYSCONFIG);
145 val = RD4(sc, UHH_HOSTCONFIG);
|
| /src/sys/arch/evbppc/wii/dev/ |
| hwgpio.c | 83 #define RD4(reg) in32(reg)
89 return (RD4(HW_GPIOB_IN) & __BIT(pin)) != 0;
99 out = RD4(HW_GPIOB_OUT);
116 dir = RD4(HW_GPIOB_DIR);
149 in = RD4(HW_GPIOB_IN);
150 out = RD4(HW_GPIOB_OUT);
151 dir = RD4(HW_GPIOB_DIR);
|
| hollywood.c | 48 #define RD4(reg) in32(reg)
96 val = RD4(HW_VERSION);
170 raw = RD4(HW_PPCIRQFLAGS);
192 val = RD4(HW_ARMIRQMASK);
227 WR4(HW_AHBPROT, RD4(HW_AHBPROT) & ~mask);
|
| /src/sys/arch/arm/rockchip/ |
| rk_i2s.c | 164 #define RD4(sc, reg) \
185 ckr = RD4(sc, I2S_CKR);
207 txcr = RD4(sc, I2S_TXCR);
218 rxcr = RD4(sc, I2S_RXCR);
258 val = RD4(sc, I2S_XFER);
265 val = RD4(sc, I2S_INTCR);
297 val = RD4(sc, I2S_XFER);
302 val = RD4(sc, I2S_INTCR);
306 val = RD4(sc, I2S_CLR);
310 while ((RD4(sc, I2S_CLR) & CLR_TXC) != 0
[all...] |
| rk_gpio.c | 112 #define RD4(sc, reg) \
212 data = RD4(sc, GPIO_EXT_PORTA_REG);
229 data = RD4(sc, GPIO_SWPORTA_DR_REG);
247 ddr = RD4(sc, GPIO_SWPORTA_DDR_REG);
268 data = RD4(sc, GPIOV2_EXT_PORT_REG);
310 status = RD4(sc, GPIO_INT_STATUS_REG);
351 val = RD4(sc, GPIO_INTTYPE_LEVEL_REG);
358 val = RD4(sc, GPIO_INT_POLARITY_REG);
365 val = RD4(sc, GPIO_INTEN_REG);
398 val = RD4(sc, GPIO_INTEN_REG)
[all...] |
| rk3399_iomux.c | 200 #define RD4(syscon, reg) \
248 printf("%s: bank %d idx %d flags %#x: %08x -> ", __func__, bank, idx, flags, RD4(syscon, reg));
252 printf("%08x (reg %#lx)\n", RD4(syscon, reg), reg);
340 printf("%s: bank %d idx %d val %d: %08x -> ", __func__, bank, idx, val, RD4(syscon, reg));
344 printf("%08x (reg %#lx)\n", RD4(syscon, reg), reg);
374 printf("%s: bank %d idx %d mux %#x: %08x -> ", __func__, bank, idx, mux, RD4(syscon, reg));
378 printf("%08x (reg %#lx)\n", RD4(syscon, reg), reg);
471 val = RD4(syscon, GRF_GPIO4B_IOMUX);
476 val = RD4(syscon, GRF_SOC_CON7);
|
| /src/sys/dev/fdt/ |
| dwc3_fdt.c | 90 #define RD4(sc, reg) \
95 WR4((sc), (reg), RD4((sc), (reg)) | (mask))
97 WR4((sc), (reg), RD4((sc), (reg)) & ~(mask))
132 val = RD4(sc, DWC3_GUSB2PHYCFG(0));
160 val = RD4(sc, DWC3_GUSB3PIPECTL(0));
169 val = RD4(sc, DWC3_GUCTL1);
179 val = RD4(sc, DWC3_DCFG);
199 val = RD4(sc, DWC3_GCTL);
319 const uint32_t snpsid = RD4(sc, DWC3_SNPSID);
|
| /src/sys/arch/arm/sunxi/ |
| sun8i_codec.c | 129 #define RD4(sc, reg) \
218 val = RD4(sc, AIF1CLK_CTRL);
290 val = RD4(sc, HMIC_CTRL1);
308 val = RD4(sc, HMIC_STS);
328 val = RD4(sc, HMIC_STS);
421 val = RD4(sc, SYSCLK_CTL);
436 val = RD4(sc, SYS_SR_CTRL);
442 val = RD4(sc, AIF1CLK_CTRL);
448 val = RD4(sc, AIF1_DACDAT_CTRL);
454 val = RD4(sc, DAC_MXR_SRC)
[all...] |
| sun4i_a10_codec.c | 108 #define RD4(sc, reg) \
113 WR4((sc), (reg), RD4((sc), (reg)) | (mask))
115 WR4((sc), (reg), RD4((sc), (reg)) & ~(mask))
160 val = RD4(sc, mix->reg);
183 val = RD4(sc, mix->reg);
|
| sun9i_a80_cpusclk.c | 80 #define RD4(sc, reg) \
176 const uint32_t val = RD4(sc, 0);
193 const uint32_t val = RD4(sc, 0);
|
| /src/sys/dev/acpi/ |
| amdgpio.c | 77 #define RD4(sc, reg) \
341 val = RD4(sc, AMDGPIO_PIN_REG(pin));
358 val = RD4(sc, AMDGPIO_PIN_REG(pin));
424 val = RD4(sc, AMDGPIO_PIN_REG(pin));
445 val = RD4(sc, AMDGPIO_PIN_REG(aih->ih_pin));
472 val = RD4(sc, AMDGPIO_PIN_REG(aih->ih_pin));
484 val = RD4(sc, AMDGPIO_PIN_REG(aih->ih_pin));
500 status = RD4(sc, AMDGPIO_INTR_STATUS(1));
502 status |= RD4(sc, AMDGPIO_INTR_STATUS(0));
517 val = RD4(sc, AMDGPIO_PIN_REG(pin))
[all...] |
| /src/sys/external/bsd/sljit/dist/sljit_src/ |
| sljitNativeARM_T2_32.c | 70 #define RD4(rd) (reg_map[rd] << 8)
209 FAIL_IF(push_inst32(compiler, MOVW | RD4(dst) |
211 return push_inst32(compiler, MOVT | RD4(dst) |
495 return push_inst32(compiler, MOV_WI | RD4(dst) | tmp);
498 return push_inst32(compiler, MVN_WI | RD4(dst) | tmp);
502 FAIL_IF(push_inst32(compiler, MOVW | RD4(dst) |
507 return push_inst32(compiler, MOVT | RD4(dst) |
567 return push_inst32(compiler, ADDWI | RD4(dst) | RN4(reg) | IMM12(imm));
569 return push_inst32(compiler, SUBWI | RD4(dst) | RN4(reg) | IMM12(nimm));
573 return push_inst32(compiler, ADD_WI | (flags & SET_FLAGS) | RD4(dst) | RN4(reg) | imm)
[all...] |
| /src/sys/arch/evbppc/wii/ |
| pic_pi.c | 54 #define RD4(reg) in32(reg)
76 raw = RD4(PI_INTSR);
|
| /src/sys/arch/arm/xilinx/ |
| zynq_xadc.c | 147 #define RD4(sc, reg) \
174 if ((RD4(sc, XADCIF_MSTS) & MSTS_CFIFOE) != 0) {
186 RD4(sc, XADCIF_RDFIFO);
210 if ((RD4(sc, XADCIF_MSTS) & MSTS_CFIFOE) != 0) {
219 val = RD4(sc, XADCIF_RDFIFO);
220 val = RD4(sc, XADCIF_RDFIFO);
231 val = RD4(sc, XADCIF_CFG);
|
| /src/sys/arch/arm/samsung/ |
| exynos_uart.c | 110 #define RD4(sc, reg) \
310 ufstat = RD4(sc, SSCOM_UFSTAT);
316 c = RD4(sc, SSCOM_URXH);
334 while ((RD4(sc, SSCOM_UFSTAT) & sc->sc_conf->txfull) != 0)
403 ucon = RD4(sc, SSCOM_UCON);
433 ucon = RD4(sc, SSCOM_UCON);
521 while ((RD4(sc, SSCOM_UFSTAT) & sc->sc_conf->txfull) != 0)
598 ack = RD4(sc, SSCOM_UTRSTAT);
600 ack = RD4(sc, SSCOM_UINTP);
606 uerstat = RD4(sc, SSCOM_UERSTAT)
[all...] |
