| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_jpeg_v1_0.c | 185 amdgpu_ring_write(ring,
187 amdgpu_ring_write(ring, 0x68e04);
189 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
190 amdgpu_ring_write(ring, 0x80010000);
204 amdgpu_ring_write(ring,
206 amdgpu_ring_write(ring, 0x68e04);
208 amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE0));
209 amdgpu_ring_write(ring, 0x00010000);
227 amdgpu_ring_write(ring,
229 amdgpu_ring_write(ring, seq)
[all...] |
| amdgpu_jpeg_v2_0.c | 467 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
469 amdgpu_ring_write(ring, 0x68e04);
471 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
473 amdgpu_ring_write(ring, 0x80010000);
485 amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
487 amdgpu_ring_write(ring, 0x68e04);
489 amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
491 amdgpu_ring_write(ring, 0x00010000);
507 amdgpu_ring_write(ring, PACKETJ(mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET,
509 amdgpu_ring_write(ring, seq)
[all...] |
| amdgpu_uvd_v6_0.c | 188 amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
493 amdgpu_ring_write(ring, tmp);
494 amdgpu_ring_write(ring, 0xFFFFF);
497 amdgpu_ring_write(ring, tmp);
498 amdgpu_ring_write(ring, 0xFFFFF);
501 amdgpu_ring_write(ring, tmp);
502 amdgpu_ring_write(ring, 0xFFFFF);
505 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
506 amdgpu_ring_write(ring, 0x8);
508 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0))
[all...] |
| amdgpu_uvd_v5_0.c | 178 amdgpu_ring_write(ring, tmp);
179 amdgpu_ring_write(ring, 0xFFFFF);
182 amdgpu_ring_write(ring, tmp);
183 amdgpu_ring_write(ring, 0xFFFFF);
186 amdgpu_ring_write(ring, tmp);
187 amdgpu_ring_write(ring, 0xFFFFF);
190 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
191 amdgpu_ring_write(ring, 0x8);
193 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
194 amdgpu_ring_write(ring, 3)
[all...] |
| amdgpu_uvd_v4_2.c | 181 amdgpu_ring_write(ring, tmp);
182 amdgpu_ring_write(ring, 0xFFFFF);
185 amdgpu_ring_write(ring, tmp);
186 amdgpu_ring_write(ring, 0xFFFFF);
189 amdgpu_ring_write(ring, tmp);
190 amdgpu_ring_write(ring, 0xFFFFF);
193 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
194 amdgpu_ring_write(ring, 0x8);
196 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
197 amdgpu_ring_write(ring, 3)
[all...] |
| amdgpu_sdma_v2_4.c | 242 amdgpu_ring_write(ring, ring->funcs->nop |
245 amdgpu_ring_write(ring, ring->funcs->nop);
266 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
269 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
270 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
271 amdgpu_ring_write(ring, ib->length_dw);
272 amdgpu_ring_write(ring, 0);
273 amdgpu_ring_write(ring, 0);
293 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
296 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2)
[all...] |
| amdgpu_uvd_v7_0.c | 198 amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
559 amdgpu_ring_write(ring, tmp);
560 amdgpu_ring_write(ring, 0xFFFFF);
564 amdgpu_ring_write(ring, tmp);
565 amdgpu_ring_write(ring, 0xFFFFF);
569 amdgpu_ring_write(ring, tmp);
570 amdgpu_ring_write(ring, 0xFFFFF);
573 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
575 amdgpu_ring_write(ring, 0x8);
577 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j
[all...] |
| amdgpu_vcn_v2_0.c | 1302 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1303 amdgpu_ring_write(ring, 0);
1304 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1305 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_START << 1));
1319 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1320 amdgpu_ring_write(ring, VCN_DEC_KMD_CMD | (VCN_DEC_CMD_PACKET_END << 1));
1338 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0));
1339 amdgpu_ring_write(ring, 0);
1357 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0));
1358 amdgpu_ring_write(ring, seq)
[all...] |
| amdgpu_vcn_v1_0.c | 1429 amdgpu_ring_write(ring,
1431 amdgpu_ring_write(ring, 0);
1432 amdgpu_ring_write(ring,
1434 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
1448 amdgpu_ring_write(ring,
1450 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
1468 amdgpu_ring_write(ring,
1470 amdgpu_ring_write(ring, seq);
1471 amdgpu_ring_write(ring,
1473 amdgpu_ring_write(ring, addr & 0xffffffff)
[all...] |
| amdgpu_si_dma.c | 78 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
79 amdgpu_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vmid, 0));
80 amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
81 amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
101 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0));
102 amdgpu_ring_write(ring, addr & 0xfffffffc);
103 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff));
104 amdgpu_ring_write(ring, seq);
108 amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0, 0));
109 amdgpu_ring_write(ring, addr & 0xfffffffc)
[all...] |
| amdgpu_cik_sdma.c | 213 amdgpu_ring_write(ring, ring->funcs->nop |
216 amdgpu_ring_write(ring, ring->funcs->nop);
238 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
239 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
240 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
241 amdgpu_ring_write(ring, ib->length_dw);
263 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
264 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
265 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
266 amdgpu_ring_write(ring, ref_and_mask); /* reference *
[all...] |
| amdgpu_sdma_v5_0.c | 243 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
244 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
245 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
246 amdgpu_ring_write(ring, 1);
248 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
370 amdgpu_ring_write(ring, ring->funcs->nop |
373 amdgpu_ring_write(ring, ring->funcs->nop);
402 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
405 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
406 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr))
[all...] |
| amdgpu_gfx_v10_0.c | 270 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
271 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
273 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
274 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
275 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
276 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
277 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
278 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
289 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
291 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 *
[all...] |
| amdgpu_sdma_v3_0.c | 416 amdgpu_ring_write(ring, ring->funcs->nop |
419 amdgpu_ring_write(ring, ring->funcs->nop);
440 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
443 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
444 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
445 amdgpu_ring_write(ring, ib->length_dw);
446 amdgpu_ring_write(ring, 0);
447 amdgpu_ring_write(ring, 0);
467 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
470 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2)
[all...] |
| amdgpu_gfx_v7_0.c | 2112 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
2113 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2114 amdgpu_ring_write(ring, 0xDEADBEEF);
2159 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2160 amdgpu_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
2163 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ);
2164 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE);
2165 amdgpu_ring_write(ring, ref_and_mask);
2166 amdgpu_ring_write(ring, ref_and_mask);
2167 amdgpu_ring_write(ring, 0x20); /* poll interval *
[all...] |
| amdgpu_gfx_v8_0.c | 861 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
862 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
863 amdgpu_ring_write(ring, 0xDEADBEEF);
4190 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4191 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4193 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4194 amdgpu_ring_write(ring, 0x80000000);
4195 amdgpu_ring_write(ring, 0x80000000);
4200 amdgpu_ring_write(ring,
4203 amdgpu_ring_write(ring
[all...] |
| amdgpu_gfx_v6_0.c | 1812 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1813 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START));
1814 amdgpu_ring_write(ring, 0xDEADBEEF);
1834 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
1835 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
1845 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1846 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1847 amdgpu_ring_write(ring, 0);
1848 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1849 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA
[all...] |
| amdgpu_gfx_v9_0.c | 755 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
756 amdgpu_ring_write(kiq_ring,
760 amdgpu_ring_write(kiq_ring,
762 amdgpu_ring_write(kiq_ring,
764 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
765 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
766 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
767 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
778 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
780 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 *
[all...] |
| amdgpu_vce_v4_0.c | 963 amdgpu_ring_write(ring, VCE_CMD_IB_VM);
964 amdgpu_ring_write(ring, vmid);
965 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
966 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
967 amdgpu_ring_write(ring, ib->length_dw);
975 amdgpu_ring_write(ring, VCE_CMD_FENCE);
976 amdgpu_ring_write(ring, addr);
977 amdgpu_ring_write(ring, upper_32_bits(addr));
978 amdgpu_ring_write(ring, seq);
979 amdgpu_ring_write(ring, VCE_CMD_TRAP)
[all...] |
| amdgpu_vce_v3_0.c | 846 amdgpu_ring_write(ring, VCE_CMD_IB_VM);
847 amdgpu_ring_write(ring, vmid);
848 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
849 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
850 amdgpu_ring_write(ring, ib->length_dw);
856 amdgpu_ring_write(ring, VCE_CMD_UPDATE_PTB);
857 amdgpu_ring_write(ring, vmid);
858 amdgpu_ring_write(ring, pd_addr >> 12);
860 amdgpu_ring_write(ring, VCE_CMD_FLUSH_TLB);
861 amdgpu_ring_write(ring, vmid)
[all...] |
| amdgpu_sdma_v4_0.c | 786 amdgpu_ring_write(ring, ring->funcs->nop |
789 amdgpu_ring_write(ring, ring->funcs->nop);
810 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
813 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
814 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
815 amdgpu_ring_write(ring, ib->length_dw);
816 amdgpu_ring_write(ring, 0);
817 amdgpu_ring_write(ring, 0);
827 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
833 amdgpu_ring_write(ring, addr0)
[all...] |
| amdgpu_jpeg.c | 125 amdgpu_ring_write(ring, PACKET0(adev->jpeg.internal.jpeg_pitch, 0));
126 amdgpu_ring_write(ring, 0xDEADBEEF);
|
| amdgpu_vce.c | 1055 amdgpu_ring_write(ring, VCE_CMD_IB);
1056 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1057 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1058 amdgpu_ring_write(ring, ib->length_dw);
1073 amdgpu_ring_write(ring, VCE_CMD_FENCE);
1074 amdgpu_ring_write(ring, addr);
1075 amdgpu_ring_write(ring, upper_32_bits(addr));
1076 amdgpu_ring_write(ring, seq);
1077 amdgpu_ring_write(ring, VCE_CMD_TRAP);
1078 amdgpu_ring_write(ring, VCE_CMD_END)
[all...] |
| amdgpu_amdkfd_gfx_v10.c | 371 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
372 amdgpu_ring_write(kiq_ring,
382 amdgpu_ring_write(kiq_ring,
384 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo);
385 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi);
386 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo);
387 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi);
|
| amdgpu_amdkfd_gfx_v9.c | 359 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
360 amdgpu_ring_write(kiq_ring,
370 amdgpu_ring_write(kiq_ring,
372 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo);
373 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi);
374 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo);
375 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi);
|
