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    Searched refs:rb_bufsz (Results 1 - 25 of 35) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_uvd_v1_0.c 271 uint32_t rb_bufsz; local in function:uvd_v1_0_start
382 rb_bufsz = order_base_2(ring->ring_size);
383 rb_bufsz = (0x1 << 8) | rb_bufsz;
384 WREG32_P(UVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);
radeon_ni_dma.c 196 u32 rb_bufsz; local in function:cayman_dma_resume
215 rb_bufsz = order_base_2(ring->ring_size / 4);
216 rb_cntl = rb_bufsz << 1;
radeon_r600_dma.c 129 u32 rb_bufsz; local in function:r600_dma_resume
136 rb_bufsz = order_base_2(ring->ring_size / 4);
137 rb_cntl = rb_bufsz << 1;
radeon_cik_sdma.c 374 u32 rb_bufsz; local in function:cik_sdma_gfx_resume
393 rb_bufsz = order_base_2(ring->ring_size / 4);
394 rb_cntl = rb_bufsz << 1;
radeon_r600.c 2690 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2752 u32 rb_bufsz; local in function:r600_cp_resume
2762 rb_bufsz = order_base_2(ring->ring_size / 8);
2763 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2814 u32 rb_bufsz; local in function:r600_ring_init
2818 rb_bufsz = order_base_2(ring_size / 8);
2819 ring_size = (1 << (rb_bufsz + 1)) * 4;
3504 u32 rb_bufsz; local in function:r600_ih_ring_init
3507 rb_bufsz = order_base_2(ring_size / 4);
3508 ring_size = (1 << rb_bufsz) * 4
3710 int rb_bufsz; local in function:r600_irq_init
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  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_cik_ih.c 114 int rb_bufsz; local in function:cik_ih_irq_init
132 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
136 (rb_bufsz << 1));
amdgpu_ih.c 49 u32 rb_bufsz; local in function:amdgpu_ih_ring_init
53 rb_bufsz = order_base_2(ring_size / 4);
54 ring_size = (1 << rb_bufsz) * 4;
amdgpu_si_ih.c 68 int rb_bufsz; local in function:si_ih_irq_init
80 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
84 (rb_bufsz << 1) |
amdgpu_cz_ih.c 115 int rb_bufsz; local in function:cz_ih_irq_init
134 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
137 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
amdgpu_iceland_ih.c 114 int rb_bufsz; local in function:iceland_ih_irq_init
134 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
137 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
amdgpu_tonga_ih.c 111 int rb_bufsz; local in function:tonga_ih_irq_init
130 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
amdgpu_uvd_v4_2.c 262 uint32_t rb_bufsz; local in function:uvd_v4_2_start
372 rb_bufsz = order_base_2(ring->ring_size);
373 rb_bufsz = (0x1 << 8) | rb_bufsz;
374 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f);
amdgpu_vcn_v2_5.c 760 uint32_t rb_bufsz, tmp; local in function:vcn_v2_5_start_dpg_mode
856 rb_bufsz = order_base_2(ring->ring_size);
857 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
892 uint32_t rb_bufsz, tmp; local in function:vcn_v2_5_start
1036 rb_bufsz = order_base_2(ring->ring_size);
1037 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1133 uint32_t offset, size, tmp, i, rb_bufsz; local in function:vcn_v2_5_sriov_start
1250 rb_bufsz = order_base_2(ring->ring_size)
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amdgpu_uvd_v5_0.c 300 uint32_t rb_bufsz, tmp; local in function:uvd_v5_0_start
397 rb_bufsz = order_base_2(ring->ring_size);
399 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
amdgpu_navi10_ih.c 83 int rb_bufsz = order_base_2(ih->ring_size / 4); local in function:navi10_ih_rb_cntl
91 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
amdgpu_vcn_v1_0.c 788 uint32_t rb_bufsz, tmp; local in function:vcn_v1_0_start_spg_mode
907 rb_bufsz = order_base_2(ring->ring_size);
908 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
962 uint32_t rb_bufsz, tmp; local in function:vcn_v1_0_start_dpg_mode
1065 rb_bufsz = order_base_2(ring->ring_size);
1066 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
amdgpu_vcn_v2_0.c 753 uint32_t rb_bufsz, tmp; local in function:vcn_v2_0_start_dpg_mode
843 rb_bufsz = order_base_2(ring->ring_size);
844 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
879 uint32_t rb_bufsz, tmp; local in function:vcn_v2_0_start
1004 rb_bufsz = order_base_2(ring->ring_size);
1005 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
amdgpu_vega10_ih.c 173 int rb_bufsz = order_base_2(ih->ring_size / 4); local in function:vega10_ih_rb_cntl
181 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
amdgpu_sdma_v2_4.c 420 u32 rb_bufsz; local in function:sdma_v2_4_gfx_resume
444 rb_bufsz = order_base_2(ring->ring_size / 4);
446 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
amdgpu_si_dma.c 139 u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz; local in function:si_dma_start
150 rb_bufsz = order_base_2(ring->ring_size / 4);
151 rb_cntl = rb_bufsz << 1;
amdgpu_cik_sdma.c 441 u32 rb_bufsz; local in function:cik_sdma_gfx_resume
467 rb_bufsz = order_base_2(ring->ring_size / 4);
468 rb_cntl = rb_bufsz << 1;
amdgpu_uvd_v6_0.c 707 uint32_t rb_bufsz, tmp; local in function:uvd_v6_0_start
816 rb_bufsz = order_base_2(ring->ring_size);
817 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
amdgpu_gfx_v10_0.c 2774 u32 rb_bufsz; local in function:gfx_v10_0_cp_gfx_resume
2790 rb_bufsz = order_base_2(ring->ring_size / 8);
2791 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2792 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2831 rb_bufsz = order_base_2(ring->ring_size / 8);
2832 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
2833 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
2984 uint32_t rb_bufsz; local in function:gfx_v10_0_gfx_mqd_init
    [all...]
amdgpu_gfx_v6_0.c 2098 u32 rb_bufsz; local in function:gfx_v6_0_cp_gfx_resume
2114 rb_bufsz = order_base_2(ring->ring_size / 8);
2115 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2195 u32 rb_bufsz; local in function:gfx_v6_0_cp_compute_resume
2203 rb_bufsz = order_base_2(ring->ring_size / 8);
2204 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2223 rb_bufsz = order_base_2(ring->ring_size / 8);
2224 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
amdgpu_sdma_v3_0.c 655 u32 rb_bufsz; local in function:sdma_v3_0_gfx_resume
682 rb_bufsz = order_base_2(ring->ring_size / 4);
684 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);

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