Searched refs:BLENDFACTOR_ZERO (Results 1 - 25 of 54) sorted by relevance

123

/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di830_render.c104 {0, 0, BLENDFACTOR_ZERO, BLENDFACTOR_ZERO},
106 {0, 0, BLENDFACTOR_ONE, BLENDFACTOR_ZERO},
108 {0, 0, BLENDFACTOR_ZERO, BLENDFACTOR_ONE},
114 {1, 0, BLENDFACTOR_DST_ALPHA, BLENDFACTOR_ZERO},
116 {0, 1, BLENDFACTOR_ZERO, BLENDFACTOR_SRC_ALPHA},
118 {1, 0, BLENDFACTOR_INV_DST_ALPHA, BLENDFACTOR_ZERO},
120 {0, 1, BLENDFACTOR_ZERO, BLENDFACTOR_INV_SRC_ALPHA},
193 sblend = BLENDFACTOR_ZERO;
368 (i830_blend_op[op].src_blend != BLENDFACTOR_ZERO)) {
[all...]
H A Di830_3d.c146 ENABLE_DST_BLND_FACTOR | DST_BLND_FACT(BLENDFACTOR_ZERO));
H A Di830_reg.h294 #define BLENDFACTOR_ZERO 0x01 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di830_render.c104 {0, 0, BLENDFACTOR_ZERO, BLENDFACTOR_ZERO},
106 {0, 0, BLENDFACTOR_ONE, BLENDFACTOR_ZERO},
108 {0, 0, BLENDFACTOR_ZERO, BLENDFACTOR_ONE},
114 {1, 0, BLENDFACTOR_DST_ALPHA, BLENDFACTOR_ZERO},
116 {0, 1, BLENDFACTOR_ZERO, BLENDFACTOR_SRC_ALPHA},
118 {1, 0, BLENDFACTOR_INV_DST_ALPHA, BLENDFACTOR_ZERO},
120 {0, 1, BLENDFACTOR_ZERO, BLENDFACTOR_INV_SRC_ALPHA},
193 sblend = BLENDFACTOR_ZERO;
368 (i830_blend_op[op].src_blend != BLENDFACTOR_ZERO)) {
[all...]
H A Di830_3d.c146 ENABLE_DST_BLND_FACTOR | DST_BLND_FACT(BLENDFACTOR_ZERO));
H A Di830_reg.h288 #define BLENDFACTOR_ZERO 0x01 macro
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di830_render.c102 {0, 0, BLENDFACTOR_ZERO, BLENDFACTOR_ZERO},
104 {0, 0, BLENDFACTOR_ONE, BLENDFACTOR_ZERO},
106 {0, 0, BLENDFACTOR_ZERO, BLENDFACTOR_ONE},
112 {1, 0, BLENDFACTOR_DST_ALPHA, BLENDFACTOR_ZERO},
114 {0, 1, BLENDFACTOR_ZERO, BLENDFACTOR_SRC_ALPHA},
116 {1, 0, BLENDFACTOR_INV_DST_ALPHA, BLENDFACTOR_ZERO},
118 {0, 1, BLENDFACTOR_ZERO, BLENDFACTOR_INV_SRC_ALPHA},
194 sblend = BLENDFACTOR_ZERO;
386 (i830_blend_op[op].src_blend != BLENDFACTOR_ZERO))
[all...]
H A Di830_3d.c153 DST_BLND_FACT(BLENDFACTOR_ZERO));
H A Di830_reg.h224 #define BLENDFACTOR_ZERO 0x01 macro
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/
H A Dswr_state.h292 return BLENDFACTOR_ZERO;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/swr/
H A Dswr_state.h315 return BLENDFACTOR_ZERO;
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen8_render.c189 /* Clear */ {0, BLENDFACTOR_ZERO, BLENDFACTOR_ZERO},
190 /* Src */ {0, BLENDFACTOR_ONE, BLENDFACTOR_ZERO},
191 /* Dst */ {0, BLENDFACTOR_ZERO, BLENDFACTOR_ONE},
194 /* In */ {0, BLENDFACTOR_DST_ALPHA, BLENDFACTOR_ZERO},
195 /* InReverse */ {1, BLENDFACTOR_ZERO, BLENDFACTOR_SRC_ALPHA},
196 /* Out */ {0, BLENDFACTOR_INV_DST_ALPHA, BLENDFACTOR_ZERO},
197 /* OutReverse */ {1, BLENDFACTOR_ZERO, BLENDFACTOR_INV_SRC_ALPHA},
216 ((d != BLENDFACTOR_ZERO) << 15 | ((s) * GEN8_BLENDFACTOR_COUNT + (d)) << 4)
218 #define NO_BLEND BLEND_OFFSET(BLENDFACTOR_ONE, BLENDFACTOR_ZERO)
[all...]
H A Dgen9_render.c206 /* Clear */ {0, BLENDFACTOR_ZERO, BLENDFACTOR_ZERO},
207 /* Src */ {0, BLENDFACTOR_ONE, BLENDFACTOR_ZERO},
208 /* Dst */ {0, BLENDFACTOR_ZERO, BLENDFACTOR_ONE},
211 /* In */ {0, BLENDFACTOR_DST_ALPHA, BLENDFACTOR_ZERO},
212 /* InReverse */ {1, BLENDFACTOR_ZERO, BLENDFACTOR_SRC_ALPHA},
213 /* Out */ {0, BLENDFACTOR_INV_DST_ALPHA, BLENDFACTOR_ZERO},
214 /* OutReverse */ {1, BLENDFACTOR_ZERO, BLENDFACTOR_INV_SRC_ALPHA},
233 ((d != BLENDFACTOR_ZERO) << 15 | ((s) * GEN9_BLENDFACTOR_COUNT + (d)) << 4)
235 #define NO_BLEND BLEND_OFFSET(BLENDFACTOR_ONE, BLENDFACTOR_ZERO)
[all...]
H A Dgen2_render.c66 {0, 0, BLENDFACTOR_ZERO, BLENDFACTOR_ZERO},
68 {0, 0, BLENDFACTOR_ONE, BLENDFACTOR_ZERO},
70 {0, 0, BLENDFACTOR_ZERO, BLENDFACTOR_ONE},
76 {1, 0, BLENDFACTOR_DST_ALPHA, BLENDFACTOR_ZERO},
78 {0, 1, BLENDFACTOR_ZERO, BLENDFACTOR_SRC_ALPHA},
80 {1, 0, BLENDFACTOR_INV_DST_ALPHA, BLENDFACTOR_ZERO},
82 {0, 1, BLENDFACTOR_ZERO, BLENDFACTOR_INV_SRC_ALPHA},
442 sblend = BLENDFACTOR_ZERO;
514 ENABLE_DST_BLND_FACTOR | DST_BLND_FACT(BLENDFACTOR_ZERO));
[all...]
H A Dgen2_render.h217 #define BLENDFACTOR_ZERO 0x01 macro
H A Dgen8_render.h370 #define BLENDFACTOR_ZERO 0x11 macro
H A Dgen9_render.h379 #define BLENDFACTOR_ZERO 0x11 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen8_render.c150 /* Clear */ {0, BLENDFACTOR_ZERO, BLENDFACTOR_ZERO},
151 /* Src */ {0, BLENDFACTOR_ONE, BLENDFACTOR_ZERO},
152 /* Dst */ {0, BLENDFACTOR_ZERO, BLENDFACTOR_ONE},
155 /* In */ {0, BLENDFACTOR_DST_ALPHA, BLENDFACTOR_ZERO},
156 /* InReverse */ {1, BLENDFACTOR_ZERO, BLENDFACTOR_SRC_ALPHA},
157 /* Out */ {0, BLENDFACTOR_INV_DST_ALPHA, BLENDFACTOR_ZERO},
158 /* OutReverse */ {1, BLENDFACTOR_ZERO, BLENDFACTOR_INV_SRC_ALPHA},
177 ((d != BLENDFACTOR_ZERO) << 15 | ((s) * GEN8_BLENDFACTOR_COUNT + (d)) << 4)
179 #define NO_BLEND BLEND_OFFSET(BLENDFACTOR_ONE, BLENDFACTOR_ZERO)
[all...]
H A Dgen2_render.c63 {0, 0, BLENDFACTOR_ZERO, BLENDFACTOR_ZERO},
65 {0, 0, BLENDFACTOR_ONE, BLENDFACTOR_ZERO},
67 {0, 0, BLENDFACTOR_ZERO, BLENDFACTOR_ONE},
73 {1, 0, BLENDFACTOR_DST_ALPHA, BLENDFACTOR_ZERO},
75 {0, 1, BLENDFACTOR_ZERO, BLENDFACTOR_SRC_ALPHA},
77 {1, 0, BLENDFACTOR_INV_DST_ALPHA, BLENDFACTOR_ZERO},
79 {0, 1, BLENDFACTOR_ZERO, BLENDFACTOR_INV_SRC_ALPHA},
439 sblend = BLENDFACTOR_ZERO;
511 ENABLE_DST_BLND_FACTOR | DST_BLND_FACT(BLENDFACTOR_ZERO));
[all...]
H A Dgen2_render.h217 #define BLENDFACTOR_ZERO 0x01 macro
H A Dgen8_render.h369 #define BLENDFACTOR_ZERO 0x11 macro
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/rasterizer/core/core/
H A Dblend.h42 case BLENDFACTOR_ZERO:
H A Dstate.h489 BLENDFACTOR_ZERO, enumerator in enum:SWR_BLEND_FACTOR
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di830_reg.h288 #define BLENDFACTOR_ZERO 0x01 macro
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di830_reg.h288 #define BLENDFACTOR_ZERO 0x01 macro

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