Searched refs:ENABLE_COLOR_BLEND (Results 1 - 19 of 19) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di830_3d.c191 DISABLE_ALPHA_TEST | ENABLE_COLOR_BLEND | DISABLE_DEPTH_TEST);
H A Di830_reg.h223 #define ENABLE_COLOR_BLEND ((1<<3)|(1<<2)) macro
H A Di830_render.c634 ENABLE_COLOR_BLEND | DISABLE_DEPTH_TEST);
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di830_3d.c191 DISABLE_ALPHA_TEST | ENABLE_COLOR_BLEND | DISABLE_DEPTH_TEST);
H A Di830_reg.h217 #define ENABLE_COLOR_BLEND ((1<<3)|(1<<2)) macro
H A Di830_render.c634 ENABLE_COLOR_BLEND | DISABLE_DEPTH_TEST);
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di830_3d.c207 ENABLE_COLOR_BLEND |
H A Di830_reg.h153 #define ENABLE_COLOR_BLEND ((1<<3)|(1<<2)) macro
H A Di830_render.c584 ENABLE_COLOR_BLEND | DISABLE_DEPTH_TEST);
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i915/
H A Di830_state.c239 i830->state.Ctx[I830_CTXREG_ENABLES_1] &= ~(ENABLE_COLOR_BLEND |
245 i830->state.Ctx[I830_CTXREG_ENABLES_1] &= ~(ENABLE_COLOR_BLEND |
247 i830->state.Ctx[I830_CTXREG_ENABLES_1] |= (ENABLE_COLOR_BLEND |
251 i830->state.Ctx[I830_CTXREG_ENABLES_1] &= ~(ENABLE_COLOR_BLEND |
H A Di830_reg.h124 #define ENABLE_COLOR_BLEND ((1<<3)|(1<<2)) macro
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i915/
H A Di830_state.c239 i830->state.Ctx[I830_CTXREG_ENABLES_1] &= ~(ENABLE_COLOR_BLEND |
245 i830->state.Ctx[I830_CTXREG_ENABLES_1] &= ~(ENABLE_COLOR_BLEND |
247 i830->state.Ctx[I830_CTXREG_ENABLES_1] |= (ENABLE_COLOR_BLEND |
251 i830->state.Ctx[I830_CTXREG_ENABLES_1] &= ~(ENABLE_COLOR_BLEND |
H A Di830_reg.h124 #define ENABLE_COLOR_BLEND ((1<<3)|(1<<2)) macro
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen2_render.h146 #define ENABLE_COLOR_BLEND ((1<<3)|(1<<2)) macro
H A Dgen2_render.c524 ENABLE_COLOR_BLEND);
657 DISABLE_LOGIC_OP | ENABLE_COLOR_BLEND);
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di830_reg.h217 #define ENABLE_COLOR_BLEND ((1<<3)|(1<<2)) macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen2_render.h146 #define ENABLE_COLOR_BLEND ((1<<3)|(1<<2)) macro
H A Dgen2_render.c521 ENABLE_COLOR_BLEND);
642 DISABLE_LOGIC_OP | ENABLE_COLOR_BLEND);
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di830_reg.h217 #define ENABLE_COLOR_BLEND ((1<<3)|(1<<2)) macro

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