Searched refs:ISL_AUX_USAGE_HIZ_CCS_WT (Results 1 - 12 of 12) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/intel/isl/
H A Disl_emit_depth_stencil.c243 info->hiz_usage == ISL_AUX_USAGE_HIZ_CCS_WT;
H A Disl_surface_state.c114 [ISL_AUX_USAGE_HIZ_CCS_WT] = AUX_CCS_E,
356 s.DepthStencilResource = info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
636 info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
H A Disl.h817 ISL_AUX_USAGE_HIZ_CCS_WT, enumerator in enum:isl_aux_usage
2084 usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
2102 usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/iris/
H A Diris_resolve.c500 case ISL_AUX_USAGE_HIZ_CCS_WT:
865 case ISL_AUX_USAGE_HIZ_CCS_WT:
1040 case ISL_AUX_USAGE_HIZ_CCS_WT:
H A Diris_blit.c562 case ISL_AUX_USAGE_HIZ_CCS_WT:
H A Diris_clear.c512 if (res->aux.usage == ISL_AUX_USAGE_HIZ_CCS_WT) {
H A Diris_resource.c767 res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ_CCS_WT;
799 case ISL_AUX_USAGE_HIZ_CCS_WT:
/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A Danv_image.c579 image->planes[plane].aux_usage = ISL_AUX_USAGE_HIZ_CCS_WT;
591 if (image->planes[plane].aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT)
2084 case ISL_AUX_USAGE_HIZ_CCS_WT:
2109 case ISL_AUX_USAGE_HIZ_CCS_WT:
H A Danv_blorp.c1788 depth.aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT) {
/xsrc/external/mit/MesaLib/dist/src/intel/blorp/
H A Dblorp_clear.c926 } else if (aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT) {
H A Dblorp_blit.c2812 params.src.aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D20.1.0.rst2380 - intel/isl: Add a separate ISL_AUX_USAGE_HIZ_CCS_WT
2382 - iris: Use ISL_AUX_USAGE_HIZ_CCS_WT to indicate write-through HiZ
2383 - intel/isl: Require ISL_AUX_USAGE_HIZ_CCS_WT for HZ+CCS WT mode

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