Searched refs:REG_TYPE_R (Results 1 - 25 of 28) sorted by relevance

12

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/i915/
H A Di915_fpc_emit.c170 if (GET_UREG_TYPE(dest) == REG_TYPE_R)
222 tempReg = UREG(REG_TYPE_R, temp); /* make i915 register */
254 if (GET_UREG_TYPE(coord) == REG_TYPE_R &&
269 if (GET_UREG_TYPE(dest) == REG_TYPE_R)
289 return swizzle(UREG(REG_TYPE_R, 0), ZERO, ZERO, ZERO, ZERO);
291 return swizzle(UREG(REG_TYPE_R, 0), ONE, ONE, ONE, ONE);
H A Di915_fpc_translate.c179 src = UREG(REG_TYPE_R, index);
299 return UREG(REG_TYPE_R, dest->Register.Index);
H A Di915_reg.h498 #define REG_TYPE_R 0 /* temporary regs, no need to macro
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/i915/
H A Di915_fpc_emit.c161 if (GET_UREG_TYPE(dest) == REG_TYPE_R)
212 tempReg = UREG(REG_TYPE_R, temp); /* make i915 register */
244 if (GET_UREG_TYPE(coord) == REG_TYPE_R &&
256 if (GET_UREG_TYPE(dest) == REG_TYPE_R)
275 return swizzle(UREG(REG_TYPE_R, 0), ZERO, ZERO, ZERO, ZERO);
277 return swizzle(UREG(REG_TYPE_R, 0), ONE, ONE, ONE, ONE);
H A Di915_fpc_translate.c61 (REG_TYPE_R << A0_SRC0_TYPE_SHIFT) | (0 << A0_SRC0_NR_SHIFT)),
147 src = UREG(REG_TYPE_R, index);
260 return UREG(REG_TYPE_R, dest->Register.Index);
534 negate(swizzle(UREG(REG_TYPE_R, 0), ONE, ONE, ONE, ONE),
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i915/
H A Di915_program.c85 return UREG(REG_TYPE_R, (bit - 1));
199 if (GET_UREG_TYPE(dest) == REG_TYPE_R)
214 return UREG(REG_TYPE_R, bit - 1);
254 if ((GET_UREG_TYPE(coord) != REG_TYPE_R) &&
275 if (GET_UREG_TYPE(coord) == REG_TYPE_R &&
291 if (GET_UREG_TYPE(dest) == REG_TYPE_R)
306 return swizzle(UREG(REG_TYPE_R, 0), ZERO, ZERO, ZERO, ZERO);
308 return swizzle(UREG(REG_TYPE_R, 0), ONE, ONE, ONE, ONE);
H A Di915_reg.h370 #define REG_TYPE_R 0 /* temporary regs, no need to macro
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i915/
H A Di915_program.c85 return UREG(REG_TYPE_R, (bit - 1));
199 if (GET_UREG_TYPE(dest) == REG_TYPE_R)
214 return UREG(REG_TYPE_R, bit - 1);
254 if ((GET_UREG_TYPE(coord) != REG_TYPE_R) &&
275 if (GET_UREG_TYPE(coord) == REG_TYPE_R &&
291 if (GET_UREG_TYPE(dest) == REG_TYPE_R)
306 return swizzle(UREG(REG_TYPE_R, 0), ZERO, ZERO, ZERO, ZERO);
308 return swizzle(UREG(REG_TYPE_R, 0), ONE, ONE, ONE, ONE);
H A Di915_reg.h370 #define REG_TYPE_R 0 /* temporary regs, no need to macro
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di915_3d.h41 #define FS_R0 ((REG_TYPE_R << 8) | 0)
42 #define FS_R1 ((REG_TYPE_R << 8) | 1)
43 #define FS_R2 ((REG_TYPE_R << 8) | 2)
44 #define FS_R3 ((REG_TYPE_R << 8) | 3)
H A Di915_reg.h507 #define REG_TYPE_R 0 /* temporary regs, no need to macro
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di915_3d.h36 #define REG_TYPE_R 0 /* temporary regs, no need to macro
245 #define FS_R0 ((REG_TYPE_R << REG_TYPE_SHIFT) | 0)
246 #define FS_R1 ((REG_TYPE_R << REG_TYPE_SHIFT) | 1)
247 #define FS_R2 ((REG_TYPE_R << REG_TYPE_SHIFT) | 2)
248 #define FS_R3 ((REG_TYPE_R << REG_TYPE_SHIFT) | 3)
H A Di915_reg.h486 #define REG_TYPE_R 0 /* temporary regs, no need to macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di915_3d.h36 #define REG_TYPE_R 0 /* temporary regs, no need to macro
245 #define FS_R0 ((REG_TYPE_R << REG_TYPE_SHIFT) | 0)
246 #define FS_R1 ((REG_TYPE_R << REG_TYPE_SHIFT) | 1)
247 #define FS_R2 ((REG_TYPE_R << REG_TYPE_SHIFT) | 2)
248 #define FS_R3 ((REG_TYPE_R << REG_TYPE_SHIFT) | 3)
H A Di915_reg.h486 #define REG_TYPE_R 0 /* temporary regs, no need to macro
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di915_program.h4 #define REG_TYPE_R 0 /* temporary regs, no need to macro
H A Di915_xvmc.c197 dest = UREG(REG_TYPE_R, 0);
205 src0 = UREG(REG_TYPE_R, 0);
229 dest = UREG(REG_TYPE_R, 0);
237 src0 = UREG(REG_TYPE_R, 0);
274 dest = UREG(REG_TYPE_R, 0);
281 dest = UREG(REG_TYPE_R, 1);
288 dest = UREG(REG_TYPE_R, 0);
289 src0 = UREG(REG_TYPE_R, 0);
290 src1 = UREG(REG_TYPE_R, 1);
298 src0 = UREG(REG_TYPE_R,
[all...]
H A Di915_reg.h486 #define REG_TYPE_R 0 /* temporary regs, no need to macro
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di915_program.h4 #define REG_TYPE_R 0 /* temporary regs, no need to macro
H A Di915_xvmc.c197 dest = UREG(REG_TYPE_R, 0);
205 src0 = UREG(REG_TYPE_R, 0);
229 dest = UREG(REG_TYPE_R, 0);
237 src0 = UREG(REG_TYPE_R, 0);
274 dest = UREG(REG_TYPE_R, 0);
281 dest = UREG(REG_TYPE_R, 1);
288 dest = UREG(REG_TYPE_R, 0);
289 src0 = UREG(REG_TYPE_R, 0);
290 src1 = UREG(REG_TYPE_R, 1);
298 src0 = UREG(REG_TYPE_R,
[all...]
H A Di915_reg.h486 #define REG_TYPE_R 0 /* temporary regs, no need to macro
/xsrc/external/mit/xf86-video-intel-old/dist/src/xvmc/
H A Di915_program.h4 #define REG_TYPE_R 0 /* temporary regs, no need to macro
H A Di915_xvmc.c240 dest = UREG(REG_TYPE_R, 0);
247 src0 = UREG(REG_TYPE_R, 0);
268 dest = UREG(REG_TYPE_R, 0);
275 src0 = UREG(REG_TYPE_R, 0);
305 dest = UREG(REG_TYPE_R, 0);
311 dest = UREG(REG_TYPE_R, 1);
317 dest = UREG(REG_TYPE_R, 0);
318 src0 = UREG(REG_TYPE_R, 0);
319 src1 = UREG(REG_TYPE_R, 1);
326 src0 = UREG(REG_TYPE_R,
[all...]
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen3_render.h489 #define REG_TYPE_R 0 /* temporary regs, no need to macro
883 #define REG_TYPE_R 0 /* temporary regs, no need to macro
1092 #define FS_R0 ((REG_TYPE_R << REG_TYPE_SHIFT) | 0)
1093 #define FS_R1 ((REG_TYPE_R << REG_TYPE_SHIFT) | 1)
1094 #define FS_R2 ((REG_TYPE_R << REG_TYPE_SHIFT) | 2)
1095 #define FS_R3 ((REG_TYPE_R << REG_TYPE_SHIFT) | 3)
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen3_render.h489 #define REG_TYPE_R 0 /* temporary regs, no need to macro
883 #define REG_TYPE_R 0 /* temporary regs, no need to macro
1092 #define FS_R0 ((REG_TYPE_R << REG_TYPE_SHIFT) | 0)
1093 #define FS_R1 ((REG_TYPE_R << REG_TYPE_SHIFT) | 1)
1094 #define FS_R2 ((REG_TYPE_R << REG_TYPE_SHIFT) | 2)
1095 #define FS_R3 ((REG_TYPE_R << REG_TYPE_SHIFT) | 3)

Completed in 106 milliseconds

12