Searched refs:address_reg (Results 1 - 12 of 12) sorted by relevance

/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di915_3d.h234 #define i915_fs_texld(dest_reg, sampler_reg, address_reg) \
236 FS_OUT(_i915_fs_texld(T0_TEXLD, dest_reg, sampler_reg, address_reg)); \
239 #define i915_fs_texldp(dest_reg, sampler_reg, address_reg) \
241 FS_OUT(_i915_fs_texld(T0_TEXLDP, dest_reg, sampler_reg, address_reg)); \
245 _i915_fs_texld(int load_op, int dest_reg, int sampler_reg, int address_reg) argument
260 op.ui[1] |= REG_TYPE(address_reg) << T1_ADDRESS_REG_TYPE_SHIFT;
261 op.ui[1] |= REG_NR(address_reg) << T1_ADDRESS_REG_NR_SHIFT;
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di915_3d.h367 #define i915_fs_texld(dest_reg, sampler_reg, address_reg) \
373 OUT_BATCH((REG_TYPE(address_reg) << T1_ADDRESS_REG_TYPE_SHIFT) | \
374 (REG_NR(address_reg) << T1_ADDRESS_REG_NR_SHIFT)); \
378 #define i915_fs_texldp(dest_reg, sampler_reg, address_reg) \
384 OUT_BATCH((REG_TYPE(address_reg) << T1_ADDRESS_REG_TYPE_SHIFT) | \
385 (REG_NR(address_reg) << T1_ADDRESS_REG_NR_SHIFT)); \
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di915_3d.h367 #define i915_fs_texld(dest_reg, sampler_reg, address_reg) \
373 OUT_BATCH((REG_TYPE(address_reg) << T1_ADDRESS_REG_TYPE_SHIFT) | \
374 (REG_NR(address_reg) << T1_ADDRESS_REG_NR_SHIFT)); \
378 #define i915_fs_texldp(dest_reg, sampler_reg, address_reg) \
384 OUT_BATCH((REG_TYPE(address_reg) << T1_ADDRESS_REG_TYPE_SHIFT) | \
385 (REG_NR(address_reg) << T1_ADDRESS_REG_NR_SHIFT)); \
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen3_render.h1214 #define gen3_fs_texld(dest_reg, sampler_reg, address_reg) \
1220 OUT_BATCH((REG_TYPE(address_reg) << T1_ADDRESS_REG_TYPE_SHIFT) | \
1221 (REG_NR(address_reg) << T1_ADDRESS_REG_NR_SHIFT)); \
1225 #define gen3_fs_texldp(dest_reg, sampler_reg, address_reg) \
1231 OUT_BATCH((REG_TYPE(address_reg) << T1_ADDRESS_REG_TYPE_SHIFT) | \
1232 (REG_NR(address_reg) << T1_ADDRESS_REG_NR_SHIFT)); \
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen3_render.h1214 #define gen3_fs_texld(dest_reg, sampler_reg, address_reg) \
1220 OUT_BATCH((REG_TYPE(address_reg) << T1_ADDRESS_REG_TYPE_SHIFT) | \
1221 (REG_NR(address_reg) << T1_ADDRESS_REG_NR_SHIFT)); \
1225 #define gen3_fs_texldp(dest_reg, sampler_reg, address_reg) \
1231 OUT_BATCH((REG_TYPE(address_reg) << T1_ADDRESS_REG_TYPE_SHIFT) | \
1232 (REG_NR(address_reg) << T1_ADDRESS_REG_NR_SHIFT)); \
/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di915_structs.h591 unsigned address_reg:5; member in struct:texture_inst::__anonea2082432508
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di915_structs.h591 unsigned address_reg:5; member in struct:texture_inst::__anona54546772508
/xsrc/external/mit/xf86-video-intel-old/dist/src/xvmc/
H A Di915_structs.h628 unsigned address_reg : 5; member in struct:texture_inst::__anon8e8c39662608
/xsrc/external/mit/MesaLib.old/dist/src/mesa/program/
H A Dir_to_mesa.cpp337 static dst_reg address_reg = dst_reg(PROGRAM_ADDRESS, WRITEMASK_X); variable in typeref:typename:dst_reg
375 emit(ir, OPCODE_ARL, address_reg, *dst.reladdr);
813 emit(ir, OPCODE_ARL, address_reg, *reg->reladdr);
/xsrc/external/mit/MesaLib/dist/src/mesa/program/
H A Dir_to_mesa.cpp338 static dst_reg address_reg = dst_reg(PROGRAM_ADDRESS, WRITEMASK_X); variable in typeref:typename:dst_reg
376 emit(ir, OPCODE_ARL, address_reg, *dst.reladdr);
740 emit(ir, OPCODE_ARL, address_reg, *reg->reladdr);
/xsrc/external/mit/MesaLib.old/dist/src/mesa/state_tracker/
H A Dst_glsl_to_tgsi.cpp398 static st_dst_reg address_reg = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X, variable in typeref:typename:st_dst_reg
465 emit_arl(ir, address_reg, *dst.reladdr);
1343 emit_arl(ir, address_reg, *reg->reladdr);
/xsrc/external/mit/MesaLib/dist/src/mesa/state_tracker/
H A Dst_glsl_to_tgsi.cpp398 static st_dst_reg address_reg = st_dst_reg(PROGRAM_ADDRESS, WRITEMASK_X, variable in typeref:typename:st_dst_reg
544 emit_arl(ir, address_reg, *dst.reladdr);
1422 emit_arl(ir, address_reg, *reg->reladdr);

Completed in 492 milliseconds