| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/ |
| H A D | si_descriptors.c | 248 bool is_stencil_sampler,
259 tex->is_depth && !si_can_sample_zs(tex, is_stencil_sampler))
288 sview->is_stencil_sampler, false);
421 (!sview || !sview->is_stencil_sampler))
453 sview->is_stencil_sampler;
542 sview->is_stencil_sampler, true);
2483 sview->is_stencil_sampler, false);
2656 sview->is_stencil_sampler, false);
245 si_sampler_view_add_buffer(struct si_context * sctx,struct pipe_resource * resource,enum radeon_bo_usage usage,bool is_stencil_sampler,bool check_mem) argument
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| H A D | si_blit.c | 449 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
766 sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
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| H A D | si_pipe.h | 598 bool is_stencil_sampler; member in struct:si_sampler_view
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| H A D | si_state.c | 4072 view->is_stencil_sampler = true;
4119 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4141 if (!view->is_stencil_sampler)
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| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/ |
| H A D | r600_blit.c | 207 bool is_stencil_sampler,
216 if (is_stencil_sampler) {
285 if (r600_can_sample_zs(tex, rview->is_stencil_sampler)) {
287 rview->is_stencil_sampler,
205 r600_blit_decompress_depth_in_place(struct r600_context * rctx,struct r600_texture * texture,bool is_stencil_sampler,unsigned first_level,unsigned last_level,unsigned first_layer,unsigned last_layer) argument
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| H A D | r600_pipe.h | 291 bool is_stencil_sampler; member in struct:r600_pipe_sampler_view
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| H A D | r600_state.c | 711 view->is_stencil_sampler = true;
713 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
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| H A D | evergreen_state.c | 959 view->is_stencil_sampler = true;
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/ |
| H A D | r600_blit.c | 207 bool is_stencil_sampler,
216 if (is_stencil_sampler) {
285 if (r600_can_sample_zs(tex, rview->is_stencil_sampler)) {
287 rview->is_stencil_sampler,
205 r600_blit_decompress_depth_in_place(struct r600_context * rctx,struct r600_texture * texture,bool is_stencil_sampler,unsigned first_level,unsigned last_level,unsigned first_layer,unsigned last_layer) argument
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| H A D | r600_pipe.h | 294 bool is_stencil_sampler; member in struct:r600_pipe_sampler_view
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| H A D | r600_state.c | 714 view->is_stencil_sampler = true;
716 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
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| H A D | evergreen_state.c | 965 view->is_stencil_sampler = true;
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/ |
| H A D | si_descriptors.c | 218 enum radeon_bo_usage usage, bool is_stencil_sampler,
229 !si_can_sample_zs(tex, is_stencil_sampler))
246 sview->is_stencil_sampler, false);
435 if (tex && tex->upgraded_depth && sview && !sview->is_stencil_sampler)
466 bool is_separate_stencil = tex->db_compatible && sview->is_stencil_sampler;
578 sview->is_stencil_sampler, true);
2423 sview->is_stencil_sampler, false);
2571 sview->is_stencil_sampler, false);
217 si_sampler_view_add_buffer(struct si_context * sctx,struct pipe_resource * resource,enum radeon_bo_usage usage,bool is_stencil_sampler,bool check_mem) argument
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| H A D | si_blit.c | 419 si_decompress_depth(sctx, tex, sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
747 si_decompress_depth(sctx, tex, sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
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| H A D | si_state.c | 4337 view->is_stencil_sampler = true;
4377 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4398 if (!view->is_stencil_sampler)
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| H A D | si_pipe.h | 681 bool is_stencil_sampler; member in struct:si_sampler_view
|