Searched refs:subnr (Results 1 - 25 of 32) sorted by relevance

12

/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_reg.h225 unsigned subnr:5; /* :1 in align16 */ member in struct:brw_reg::__anon249c940f010a::__anon249c940f0208
384 * \param subnr register sub number
397 unsigned subnr,
423 reg.subnr = subnr * type_sz(type);
427 * set swizzle and writemask to W, as the lower bits of subnr will
444 brw_vec16_reg(enum brw_reg_file file, unsigned nr, unsigned subnr) argument
448 subnr,
461 brw_vec8_reg(enum brw_reg_file file, unsigned nr, unsigned subnr) argument
465 subnr,
395 brw_reg(enum brw_reg_file file,unsigned nr,unsigned subnr,unsigned negate,unsigned abs,enum brw_reg_type type,unsigned vstride,unsigned width,unsigned hstride,unsigned swizzle,unsigned writemask) argument
478 brw_vec4_reg(enum brw_reg_file file,unsigned nr,unsigned subnr) argument
495 brw_vec2_reg(enum brw_reg_file file,unsigned nr,unsigned subnr) argument
512 brw_vec1_reg(enum brw_reg_file file,unsigned nr,unsigned subnr) argument
528 brw_vecn_reg(unsigned width,enum brw_reg_file file,unsigned nr,unsigned subnr) argument
593 brw_uw16_reg(enum brw_reg_file file,unsigned nr,unsigned subnr) argument
600 brw_uw8_reg(enum brw_reg_file file,unsigned nr,unsigned subnr) argument
607 brw_uw1_reg(enum brw_reg_file file,unsigned nr,unsigned subnr) argument
613 brw_ud1_reg(enum brw_reg_file file,unsigned nr,unsigned subnr) argument
764 brw_vec1_grf(unsigned nr,unsigned subnr) argument
771 brw_vec2_grf(unsigned nr,unsigned subnr) argument
778 brw_vec4_grf(unsigned nr,unsigned subnr) argument
785 brw_vec8_grf(unsigned nr,unsigned subnr) argument
792 brw_vec16_grf(unsigned nr,unsigned subnr) argument
798 brw_vecn_grf(unsigned width,unsigned nr,unsigned subnr) argument
805 brw_uw8_grf(unsigned nr,unsigned subnr) argument
811 brw_uw16_grf(unsigned nr,unsigned subnr) argument
831 brw_address_reg(unsigned subnr) argument
879 brw_cr0_reg(unsigned subnr) argument
885 brw_sr0_reg(unsigned subnr) argument
917 brw_mask_reg(unsigned subnr) argument
935 brw_mask_stack_reg(unsigned subnr) argument
943 brw_mask_stack_depth_reg(unsigned subnr) argument
956 brw_uvec_mrf(unsigned width,unsigned nr,unsigned subnr) argument
1139 brw_vec4_indirect(unsigned subnr,int offset) argument
1149 brw_vec1_indirect(unsigned subnr,int offset) argument
1159 brw_VxH_indirect(unsigned subnr,int offset) argument
[all...]
H A Dbrw_ir.h72 using brw_reg::subnr;
H A Dbrw_ir_vec4.h86 const unsigned suboffset = reg->subnr + bytes;
88 reg->subnr = suboffset % REG_SIZE;
89 assert(reg->subnr % 16 == 0);
236 (r.file == ARF || r.file == FIXED_GRF ? r.subnr : 0);
H A Dbrw_eu_emit.c118 assert(dest.subnr == 0);
132 assert(dest.subnr % 16 == 0);
137 brw_inst_set_dst_da16_subreg_nr(devinfo, inst, dest.subnr / 16);
147 brw_inst_set_dst_da1_subreg_nr(devinfo, inst, dest.subnr);
152 brw_inst_set_dst_da16_subreg_nr(devinfo, inst, dest.subnr / 16);
165 brw_inst_set_dst_ia_subreg_nr(devinfo, inst, dest.subnr);
239 assert(reg.subnr == 0);
251 assert(reg.subnr % 16 == 0);
257 brw_inst_set_src0_da16_subreg_nr(devinfo, inst, reg.subnr / 16);
284 brw_inst_set_src0_da1_subreg_nr(devinfo, inst, reg.subnr);
[all...]
H A Dbrw_ir_fs.h91 const unsigned suboffset = reg.subnr + delta;
93 reg.subnr = suboffset % REG_SIZE;
185 (r.file == ARF || r.file == FIXED_GRF ? r.subnr : 0);
H A Dbrw_vec4.cpp703 assert(inst->src[0].subnr == 0);
1639 fprintf(file, "a0.%d", inst->dst.subnr);
1642 fprintf(file, "acc%d", inst->dst.subnr);
1645 fprintf(file, "f%d.%d", inst->dst.nr & 0xf, inst->dst.subnr);
1648 fprintf(file, "arf%d.%d", inst->dst.nr & 0xf, inst->dst.subnr);
1693 fprintf(file, "g%d.%d", inst->src[i].nr, inst->src[i].subnr);
1733 fprintf(file, "a0.%d", inst->src[i].subnr);
1736 fprintf(file, "acc%d", inst->src[i].subnr);
1739 fprintf(file, "f%d.%d", inst->src[i].nr & 0xf, inst->src[i].subnr);
1742 fprintf(file, "arf%d.%d", inst->src[i].nr & 0xf, inst->src[i].subnr);
[all...]
H A Dbrw_vec4_generator.cpp1413 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr * (REG_SIZE / 2);
1422 reg.subnr = (imm_byte_offset / (REG_SIZE / 2)) % 2;
1437 * the subnr (probably 0) to an align1 subnr and add in the swizzle.
1440 indirect.subnr = (indirect.subnr * 4 + BRW_GET_SWZ(indirect.swizzle, 0));
1446 indirect.subnr *= 2;
1479 bit_mask_in.subnr += BRW_GET_SWZ(bit_mask_in.swizzle, 0) * 4;
2102 dst.subnr = offset * 4;
2108 src[0].subnr
[all...]
H A Dbrw_fs_copy_propagation.cpp655 inst->src[arg].subnr = entry->src.subnr;
/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dbrw_reg.h225 unsigned subnr:5; /* :1 in align16 */ member in struct:brw_reg::__anoncc4238bc010a::__anoncc4238bc0208
391 * \param subnr register sub number
404 unsigned subnr,
430 reg.subnr = subnr * type_sz(type);
434 * set swizzle and writemask to W, as the lower bits of subnr will
451 brw_vec16_reg(enum brw_reg_file file, unsigned nr, unsigned subnr) argument
455 subnr,
468 brw_vec8_reg(enum brw_reg_file file, unsigned nr, unsigned subnr) argument
472 subnr,
402 brw_reg(enum brw_reg_file file,unsigned nr,unsigned subnr,unsigned negate,unsigned abs,enum brw_reg_type type,unsigned vstride,unsigned width,unsigned hstride,unsigned swizzle,unsigned writemask) argument
485 brw_vec4_reg(enum brw_reg_file file,unsigned nr,unsigned subnr) argument
502 brw_vec2_reg(enum brw_reg_file file,unsigned nr,unsigned subnr) argument
519 brw_vec1_reg(enum brw_reg_file file,unsigned nr,unsigned subnr) argument
535 brw_vecn_reg(unsigned width,enum brw_reg_file file,unsigned nr,unsigned subnr) argument
600 brw_uw16_reg(enum brw_reg_file file,unsigned nr,unsigned subnr) argument
607 brw_uw8_reg(enum brw_reg_file file,unsigned nr,unsigned subnr) argument
614 brw_uw1_reg(enum brw_reg_file file,unsigned nr,unsigned subnr) argument
620 brw_ud1_reg(enum brw_reg_file file,unsigned nr,unsigned subnr) argument
771 brw_vec1_grf(unsigned nr,unsigned subnr) argument
778 brw_vec2_grf(unsigned nr,unsigned subnr) argument
785 brw_vec4_grf(unsigned nr,unsigned subnr) argument
792 brw_vec8_grf(unsigned nr,unsigned subnr) argument
799 brw_vec16_grf(unsigned nr,unsigned subnr) argument
805 brw_vecn_grf(unsigned width,unsigned nr,unsigned subnr) argument
812 brw_uw8_grf(unsigned nr,unsigned subnr) argument
818 brw_uw16_grf(unsigned nr,unsigned subnr) argument
838 brw_address_reg(unsigned subnr) argument
886 brw_cr0_reg(unsigned subnr) argument
892 brw_sr0_reg(unsigned subnr) argument
924 brw_mask_reg(unsigned subnr) argument
948 brw_uvec_mrf(unsigned width,unsigned nr,unsigned subnr) argument
1125 brw_vec4_indirect(unsigned subnr,int offset) argument
1135 brw_vec1_indirect(unsigned subnr,int offset) argument
1145 brw_VxH_indirect(unsigned subnr,int offset) argument
[all...]
H A Dbrw_ir_vec4.h86 const unsigned suboffset = reg->subnr + bytes;
88 reg->subnr = suboffset % REG_SIZE;
89 assert(reg->subnr % 16 == 0);
236 (r.file == ARF || r.file == FIXED_GRF ? r.subnr : 0);
H A Dbrw_vec4_tes.cpp80 if (is_64bit && grf.subnr > 0) {
87 grf.subnr = 0;
H A Dbrw_eu_emit.c115 assert(dest.subnr % 16 == 0);
120 brw_inst_set_dst_da16_subreg_nr(devinfo, inst, dest.subnr / 16);
130 brw_inst_set_dst_da1_subreg_nr(devinfo, inst, dest.subnr);
135 brw_inst_set_dst_da16_subreg_nr(devinfo, inst, dest.subnr / 16);
148 brw_inst_set_dst_ia_subreg_nr(devinfo, inst, dest.subnr);
221 assert(reg.subnr % 16 == 0);
226 brw_inst_set_src0_da16_subreg_nr(devinfo, inst, reg.subnr / 16);
253 brw_inst_set_src0_da1_subreg_nr(devinfo, inst, reg.subnr);
255 brw_inst_set_src0_da16_subreg_nr(devinfo, inst, reg.subnr / 16);
258 brw_inst_set_src0_ia_subreg_nr(devinfo, inst, reg.subnr);
[all...]
H A Dbrw_ir_fs.h91 const unsigned suboffset = reg.subnr + delta;
93 reg.subnr = suboffset % REG_SIZE;
185 (r.file == ARF || r.file == FIXED_GRF ? r.subnr : 0);
H A Dbrw_shader.h78 using brw_reg::subnr;
H A Dbrw_vec4.cpp702 assert(inst->src[0].subnr == 0);
1653 fprintf(file, "a0.%d", inst->dst.subnr);
1656 fprintf(file, "acc%d", inst->dst.subnr);
1659 fprintf(file, "f%d.%d", inst->dst.nr & 0xf, inst->dst.subnr);
1662 fprintf(file, "arf%d.%d", inst->dst.nr & 0xf, inst->dst.subnr);
1707 fprintf(file, "g%d.%d", inst->src[i].nr, inst->src[i].subnr);
1747 fprintf(file, "a0.%d", inst->src[i].subnr);
1750 fprintf(file, "acc%d", inst->src[i].subnr);
1753 fprintf(file, "f%d.%d", inst->src[i].nr & 0xf, inst->src[i].subnr);
1756 fprintf(file, "arf%d.%d", inst->src[i].nr & 0xf, inst->src[i].subnr);
[all...]
H A Dbrw_vec4_generator.cpp1436 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr * (REG_SIZE / 2);
1445 reg.subnr = (imm_byte_offset / (REG_SIZE / 2)) % 2;
1460 * the subnr (probably 0) to an align1 subnr and add in the swizzle.
1463 indirect.subnr = (indirect.subnr * 4 + BRW_GET_SWZ(indirect.swizzle, 0));
1469 indirect.subnr *= 2;
2047 dst.subnr = offset * 4;
2053 src[0].subnr = 16;
2054 dst.subnr
[all...]
H A Dbrw_fs_generator.cpp428 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr;
434 reg.subnr = imm_byte_offset % REG_SIZE;
587 brw_ADD(p, addr, addr, brw_imm_uw(src.nr * REG_SIZE + src.subnr));
1995 src[0].subnr = 0 * type_sz(src[0].type);
2000 src[0].subnr = 4 * type_sz(src[0].type);
/xsrc/external/mit/xf86-video-intel/dist/src/sna/brw/
H A Dbrw_eu.h569 unsigned dest_subreg_nr:3; /* subnr for the address reg a0.x */
1132 unsigned subnr:5; /* :1 in align16 */ member in struct:brw_reg
1212 * \param subnr register sub number
1222 unsigned subnr,
1241 reg.subnr = subnr * type_sz(type);
1251 * set swizzle and writemask to W, as the lower bits of subnr will
1266 unsigned subnr)
1270 subnr,
1282 unsigned subnr)
1220 brw_reg(unsigned file,unsigned nr,unsigned subnr,unsigned type,unsigned vstride,unsigned width,unsigned hstride,unsigned swizzle,unsigned writemask) argument
1264 brw_vec16_reg(unsigned file,unsigned nr,unsigned subnr) argument
1280 brw_vec8_reg(unsigned file,unsigned nr,unsigned subnr) argument
1296 brw_vec4_reg(unsigned file,unsigned nr,unsigned subnr) argument
1312 brw_vec2_reg(unsigned file,unsigned nr,unsigned subnr) argument
1328 brw_vec1_reg(unsigned file,unsigned nr,unsigned subnr) argument
1398 brw_uw16_reg(unsigned file,unsigned nr,unsigned subnr) argument
1406 brw_uw8_reg(unsigned file,unsigned nr,unsigned subnr) argument
1414 brw_uw1_reg(unsigned file,unsigned nr,unsigned subnr) argument
1526 brw_vec1_grf(unsigned nr,unsigned subnr) argument
1532 brw_vec2_grf(unsigned nr,unsigned subnr) argument
1538 brw_vec4_grf(unsigned nr,unsigned subnr) argument
1544 brw_vec8_grf(unsigned nr,unsigned subnr) argument
1549 brw_uw8_grf(unsigned nr,unsigned subnr) argument
1554 brw_uw16_grf(unsigned nr,unsigned subnr) argument
1567 brw_address_reg(unsigned subnr) argument
1618 brw_mask_reg(unsigned subnr) argument
1631 brw_message4_reg(unsigned nr,int subnr) argument
1752 brw_vec4_indirect(unsigned subnr,int offset) argument
1762 brw_vec1_indirect(unsigned subnr,int offset) argument
[all...]
H A Dbrw_eu_emit.c117 insn->bits1.da1.dest_subreg_nr = dest.subnr;
122 insn->bits1.da16.dest_subreg_nr = dest.subnr / 16;
128 insn->bits1.ia1.dest_subreg_nr = dest.subnr;
261 insn->bits2.da1.src0_subreg_nr = reg.subnr;
264 insn->bits2.da16.src0_subreg_nr = reg.subnr / 16;
268 insn->bits2.ia1.src0_subreg_nr = reg.subnr;
334 insn->bits3.da1.src1_subreg_nr = reg.subnr;
337 insn->bits3.da16.src1_subreg_nr = reg.subnr / 16;
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/brw/
H A Dbrw_eu.h569 unsigned dest_subreg_nr:3; /* subnr for the address reg a0.x */
1132 unsigned subnr:5; /* :1 in align16 */ member in struct:brw_reg
1212 * \param subnr register sub number
1222 unsigned subnr,
1241 reg.subnr = subnr * type_sz(type);
1251 * set swizzle and writemask to W, as the lower bits of subnr will
1266 unsigned subnr)
1270 subnr,
1282 unsigned subnr)
1220 brw_reg(unsigned file,unsigned nr,unsigned subnr,unsigned type,unsigned vstride,unsigned width,unsigned hstride,unsigned swizzle,unsigned writemask) argument
1264 brw_vec16_reg(unsigned file,unsigned nr,unsigned subnr) argument
1280 brw_vec8_reg(unsigned file,unsigned nr,unsigned subnr) argument
1296 brw_vec4_reg(unsigned file,unsigned nr,unsigned subnr) argument
1312 brw_vec2_reg(unsigned file,unsigned nr,unsigned subnr) argument
1328 brw_vec1_reg(unsigned file,unsigned nr,unsigned subnr) argument
1398 brw_uw16_reg(unsigned file,unsigned nr,unsigned subnr) argument
1406 brw_uw8_reg(unsigned file,unsigned nr,unsigned subnr) argument
1414 brw_uw1_reg(unsigned file,unsigned nr,unsigned subnr) argument
1526 brw_vec1_grf(unsigned nr,unsigned subnr) argument
1532 brw_vec2_grf(unsigned nr,unsigned subnr) argument
1538 brw_vec4_grf(unsigned nr,unsigned subnr) argument
1544 brw_vec8_grf(unsigned nr,unsigned subnr) argument
1549 brw_uw8_grf(unsigned nr,unsigned subnr) argument
1554 brw_uw16_grf(unsigned nr,unsigned subnr) argument
1567 brw_address_reg(unsigned subnr) argument
1618 brw_mask_reg(unsigned subnr) argument
1631 brw_message4_reg(unsigned nr,int subnr) argument
1752 brw_vec4_indirect(unsigned subnr,int offset) argument
1762 brw_vec1_indirect(unsigned subnr,int offset) argument
[all...]
H A Dbrw_eu_emit.c117 insn->bits1.da1.dest_subreg_nr = dest.subnr;
122 insn->bits1.da16.dest_subreg_nr = dest.subnr / 16;
128 insn->bits1.ia1.dest_subreg_nr = dest.subnr;
261 insn->bits2.da1.src0_subreg_nr = reg.subnr;
264 insn->bits2.da16.src0_subreg_nr = reg.subnr / 16;
268 insn->bits2.ia1.src0_subreg_nr = reg.subnr;
334 insn->bits3.da1.src1_subreg_nr = reg.subnr;
337 insn->bits3.da16.src1_subreg_nr = reg.subnr / 16;
/xsrc/external/mit/MesaLib/dist/src/intel/tools/
H A Di965_gram.y98 reg->subnr,
1015 brw_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $5.subnr);
1524 $$.subnr = $$.subnr * brw_reg_type_to_size($4);
1535 $$.subnr = $$.subnr * brw_reg_type_to_size($4);
1691 $1.subnr,
1728 $3.subnr,
1757 $3.subnr,
1775 $$.subnr
[all...]
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen8_eu.c346 __gen8_set_dst_da1_subreg_nr(inst, reg.subnr);
354 assert(reg.subnr == 0 || reg.subnr == 16);
355 __gen8_set_dst_da16_subreg_nr(inst, reg.subnr >> 4);
469 __gen8_set_src0_da1_subreg_nr(inst, reg.subnr);
482 assert(reg.subnr == 0 || reg.subnr == 16);
483 __gen8_set_src0_da16_subreg_nr(inst, reg.subnr >> 4);
540 __gen8_set_src1_da1_subreg_nr(inst, reg.subnr);
553 assert(reg.subnr
[all...]
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen8_eu.c346 __gen8_set_dst_da1_subreg_nr(inst, reg.subnr);
354 assert(reg.subnr == 0 || reg.subnr == 16);
355 __gen8_set_dst_da16_subreg_nr(inst, reg.subnr >> 4);
469 __gen8_set_src0_da1_subreg_nr(inst, reg.subnr);
482 assert(reg.subnr == 0 || reg.subnr == 16);
483 __gen8_set_src0_da16_subreg_nr(inst, reg.subnr >> 4);
540 __gen8_set_src1_da1_subreg_nr(inst, reg.subnr);
553 assert(reg.subnr
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A Dbrw_ff_gs_emit.c439 vertex_slot.subnr = (slot % 2) * 16;

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