Searched refs:CLK_UART0 (Results 1 - 25 of 28) sorted by relevance
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| /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/ |
| H A D | exynos5410.h | 38 #define CLK_UART0 257 macro
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| H A D | actions,s500-cmu.h | 60 #define CLK_UART0 38 macro
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| H A D | actions,s700-cmu.h | 60 #define CLK_UART0 36 macro
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| H A D | actions,s900-cmu.h | 87 #define CLK_UART0 67 macro
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| H A D | pistachio-clk.h | 41 #define CLK_UART0 48 macro
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| H A D | sophgo,cv1800.h | 90 #define CLK_UART0 77 macro
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| H A D | exynos5250.h | 95 #define CLK_UART0 289 macro
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| H A D | s5pv210.h | 163 #define CLK_UART0 143 macro
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| H A D | exynos5420.h | 68 #define CLK_UART0 257 macro
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| H A D | exynos3250.h | 224 #define CLK_UART0 216 macro
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| H A D | exynos4.h | 152 #define CLK_UART0 312 macro
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| H A D | sprd,sc9860-clk.h | 87 #define CLK_UART0 2 macro
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| H A D | sprd,ums512-clk.h | 141 #define CLK_UART0 11 macro
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| H A D | rockchip,rk3588-cru.h | 683 #define CLK_UART0 666 macro
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| /src/sys/arch/mips/ingenic/ |
| H A D | apbus.c | 76 { "com", JZ_UART0, 51, CLK_UART0, 0, 0},
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| H A D | ingenic_regs.h | 169 #define CLK_UART0 (1 << 15) macro
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| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/actions/ |
| H A D | s700.dtsi | 119 clocks = <&cmu CLK_UART0>;
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| H A D | s900.dtsi | 125 clocks = <&cmu CLK_UART0>;
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| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/samsung/ |
| H A D | s5pv210.dtsi | 321 clocks = <&clocks CLK_UART0>, <&clocks CLK_UART0>,
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| H A D | exynos5410.dtsi | 340 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
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| H A D | exynos3250.dtsi | 683 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
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| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/sprd/ |
| H A D | whale2.dtsi | 78 <&ap_clk CLK_UART0>,
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| /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/actions/ |
| H A D | owl-s500.dtsi | 136 clocks = <&cmu CLK_UART0>;
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| /src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/sophgo/ |
| H A D | cv18xx.dtsi | 195 clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
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| /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/img/ |
| H A D | pistachio.dtsi | 257 clocks = <&clk_core CLK_UART0>, <&cr_periph SYS_CLK_UART0>;
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