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    Searched refs:SMU__NUM_SCLK_DPM_STATE (Results 1 - 22 of 22) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
ci_smumgr.h 28 #define SMU__NUM_SCLK_DPM_STATE 8
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
kv_dpm.h 28 #define SMU__NUM_SCLK_DPM_STATE 8
159 SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE];
amdgpu_kv_dpm.c 2883 if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
3305 if (pl_index < SMU__NUM_SCLK_DPM_STATE) {
  /src/sys/external/bsd/drm2/dist/drm/radeon/
kv_dpm.h 28 #define SMU__NUM_SCLK_DPM_STATE 8
133 SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE];
smu7.h 43 #define SMU7_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV
ci_dpm.h 31 #define SMU__NUM_SCLK_DPM_STATE 8
smu7_fusion.h 235 SMU7_Fusion_GraphicsLevel GraphicsLevel [SMU__NUM_SCLK_DPM_STATE];
smu7_discrete.h 237 SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
radeon_kv_dpm.c 2819 if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
2842 if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
smu7.h 43 #define SMU7_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV
smu71.h 33 #define SMU__NUM_SCLK_DPM_STATE 8
63 #define SMU71_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE
smu72.h 33 #define SMU__NUM_SCLK_DPM_STATE 8
111 #define SMU72_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE /* SCLK + SQ DPM + ULV */
smu73.h 95 #define SMU__NUM_SCLK_DPM_STATE 8
110 #define SMU73_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE // SCLK + SQ DPM + ULV
smu7_fusion.h 235 SMU7_Fusion_GraphicsLevel GraphicsLevel [SMU__NUM_SCLK_DPM_STATE];
smu74.h 34 #define SMU__NUM_SCLK_DPM_STATE 8
136 #define SMU74_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE /* SCLK + SQ DPM + ULV */
smu75.h 42 #define SMU__NUM_SCLK_DPM_STATE 8
57 #define SMU75_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE
smu71_discrete.h 181 SMU71_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
smu7_discrete.h 237 SMU7_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
smu72_discrete.h 168 SMU72_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
smu73_discrete.h 158 SMU73_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
smu74_discrete.h 181 SMU74_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
smu75_discrete.h 194 SMU75_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];

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