Searched refs:regid (Results 1 - 25 of 63) sorted by relevance

123

/xsrc/external/mit/MesaLib.old/dist/src/freedreno/ir3/
H A Dir3_shader.c73 * regid's might not even be valid)
81 if (v->inputs[i].regid >= regid(48,0))
86 int32_t regid = v->inputs[i].regid + n; local in function:fixup_regfootprint
89 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
91 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
94 v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
100 int32_t regid = v->outputs[i].regid local in function:fixup_regfootprint
312 uint32_t regid; local in function:dump_output
323 uint8_t regid; local in function:ir3_shader_disasm
368 uint8_t regid = so->outputs[i].regid; local in function:ir3_shader_disasm
376 uint8_t regid = so->inputs[i].regid; local in function:ir3_shader_disasm
388 uint8_t regid = so->outputs[i].regid; local in function:ir3_shader_disasm
396 uint8_t regid = so->inputs[i].regid; local in function:ir3_shader_disasm
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H A Dir3_shader.h377 * + From the vert shader, we only need the output regid
392 uint8_t regid; member in struct:ir3_shader_variant::__anon6c2d57490508
403 uint8_t regid; member in struct:ir3_shader_variant::__anon6c2d57490608
603 uint8_t regid; member in struct:ir3_shader_linkage::__anon6c2d57490a08
610 ir3_link_add(struct ir3_shader_linkage *l, uint8_t regid, uint8_t compmask, uint8_t loc) argument
616 l->var[i].regid = regid;
640 ir3_link_add(l, vs->outputs[k].regid,
651 return so->outputs[j].regid;
652 return regid(6
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H A Dir3_legalize.c174 if (last_rel && (reg->num == regid(REG_A0, 0))) {
291 ir3_reg_create(baryf, regid(63, 0), 0);
293 ir3_reg_create(baryf, regid(0, 0), 0);
/xsrc/external/mit/MesaLib/dist/src/freedreno/ir3/
H A Dir3_shader.c69 * regid's might not even be valid)
77 if (v->inputs[i].regid >= regid(48, 0))
82 int32_t regid = v->inputs[i].regid + n; local in function:fixup_regfootprint
85 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
87 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
90 v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
97 if (!VALIDREG(v->outputs[i].regid))
99 int32_t regid local in function:fixup_regfootprint
113 int32_t regid = v->sampler_prefetch[i].dst + n; local in function:fixup_regfootprint
621 uint32_t regid; local in function:dump_output
663 uint8_t regid; local in function:ir3_shader_disasm
707 uint8_t regid = so->outputs[i].regid; local in function:ir3_shader_disasm
716 uint8_t regid = so->inputs[i].regid; local in function:ir3_shader_disasm
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H A Dir3_shader.h454 /* Represents half register in regid */
549 * + From the vert shader, we only need the output regid
565 uint8_t regid; member in struct:ir3_shader_variant::__anon448bd35c0508
589 uint8_t regid; member in struct:ir3_shader_variant::__anon448bd35c0608
879 uint8_t regid; member in struct:ir3_shader_linkage::__anon448bd35c0808
905 if (regid_ != regid(63, 0)) {
909 l->var[i].regid = regid_;
928 const unsigned default_regid = pack_vs_out ? regid(63, 0) : regid(0, 0);
962 ir3_link_add(l, k >= 0 ? vs->outputs[k].regid
973 uint32_t regid = so->outputs[j].regid; local in function:ir3_find_output_regid
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H A Dir3_legalize.c215 if (last_rel && (reg->num == regid(REG_A0, 0))) {
319 ir3_dst_create(baryf, regid(63, 0), 0);
321 ir3_src_create(baryf, regid(0, 0), 0);
349 ir3_dst_create(baryf, regid(63, 0), 0)->flags |= IR3_REG_EI;
351 ir3_src_create(baryf, regid(0, 0), 0);
687 ir3_src_create(br1, regid(REG_P0, 0), 0)->def =
694 ir3_src_create(br2, regid(REG_P0, 0), 0)->def =
H A Dir3_cp_postsched.c67 (instr->dsts[0]->num == regid(REG_A0, 0)))
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_const.c32 /* regid: base const register
38 const struct ir3_shader_variant *v, uint32_t regid,
41 emit_const_asserts(ring, v, regid, sizedwords);
52 CP_LOAD_STATE6_0(.dst_off = regid / 4, .state_type = ST6_CONSTANTS,
60 CP_LOAD_STATE6_0(.dst_off = regid / 4, .state_type = ST6_CONSTANTS,
69 const struct ir3_shader_variant *v, uint32_t regid,
72 uint32_t dst_off = regid / 4;
77 emit_const_asserts(ring, v, regid, sizedwords);
116 const unsigned regid = const_state->offsets.primitive_param * 4 + 4; local in function:emit_tess_bos
120 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid /
37 fd6_emit_const_user(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,uint32_t regid,uint32_t sizedwords,const uint32_t * dwords) argument
68 fd6_emit_const_bo(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,uint32_t regid,uint32_t offset,uint32_t sizedwords,struct fd_bo * bo) argument
133 const unsigned regid = const_state->offsets.primitive_param; local in function:emit_stage_tess_consts
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H A Dfd6_compute.c91 A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
92 A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
94 OUT_RING(ring, A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
100 A6XX_SP_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
101 A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
103 OUT_RING(ring, A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
H A Dfd6_program.c213 if (l->var[idx].regid == v->outputs[k].regid)
348 return regid(63, 0);
403 vs_primitive_regid = regid(63, 0);
422 tess_coord_x_regid = regid(63, 0);
423 tess_coord_y_regid = regid(63, 0);
424 hs_rel_patch_regid = regid(63, 0);
425 ds_rel_patch_regid = regid(63, 0);
426 ds_primitive_regid = regid(63, 0);
427 hs_invocation_regid = regid(6
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a4xx/
H A Dfd4_emit.c50 /* regid: base const register
56 const struct ir3_shader_variant *v, uint32_t regid,
59 emit_const_asserts(ring, v, regid, sizedwords);
62 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid / 4) |
74 const struct ir3_shader_variant *v, uint32_t regid,
77 uint32_t dst_off = regid / 4;
82 emit_const_asserts(ring, v, regid, sizedwords);
94 uint32_t regid, uint32_t num, struct fd_bo **bos,
100 debug_assert((regid % 4) == 0);
103 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid /
55 fd4_emit_const_user(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,uint32_t regid,uint32_t sizedwords,const uint32_t * dwords) argument
73 fd4_emit_const_bo(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,uint32_t regid,uint32_t offset,uint32_t sizedwords,struct fd_bo * bo) argument
93 fd4_emit_const_ptrs(struct fd_ringbuffer * ring,gl_shader_stage type,uint32_t regid,uint32_t num,struct fd_bo ** bos,uint32_t * offsets) argument
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a4xx/
H A Dfd4_emit.c46 /* regid: base const register
52 uint32_t regid, uint32_t offset, uint32_t sizedwords,
58 debug_assert((regid % 4) == 0);
70 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
90 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
95 debug_assert((regid % 4) == 0);
98 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid/4) |
369 unsigned vertex_regid = regid(63, 0);
370 unsigned instance_regid = regid(63, 0);
371 unsigned vtxcnt_regid = regid(6
51 fd4_emit_const(struct fd_ringbuffer * ring,gl_shader_stage type,uint32_t regid,uint32_t offset,uint32_t sizedwords,const uint32_t * dwords,struct pipe_resource * prsc) argument
89 fd4_emit_const_bo(struct fd_ringbuffer * ring,gl_shader_stage type,boolean write,uint32_t regid,uint32_t num,struct pipe_resource ** prscs,uint32_t * offsets) argument
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H A Dfd4_program.c221 if (pos_regid == regid(63, 0)) {
226 pos_regid = regid(0, 0);
247 zwcoord_regid = (coord_regid == regid(63,0)) ? regid(63,0) : (coord_regid + 2);
336 reg |= A4XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
340 reg |= A4XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a3xx/
H A Dfd3_emit.c55 /* regid: base const register
61 const struct ir3_shader_variant *v, uint32_t regid,
64 emit_const_asserts(ring, v, regid, sizedwords);
67 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid / 2) |
79 const struct ir3_shader_variant *v, uint32_t regid,
82 uint32_t dst_off = regid / 2;
91 emit_const_asserts(ring, v, regid, sizedwords);
103 uint32_t regid, uint32_t num, struct fd_bo **bos,
109 debug_assert((regid % 4) == 0);
112 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid /
60 fd3_emit_const_user(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,uint32_t regid,uint32_t sizedwords,const uint32_t * dwords) argument
78 fd3_emit_const_bo(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,uint32_t regid,uint32_t offset,uint32_t sizedwords,struct fd_bo * bo) argument
102 fd3_emit_const_ptrs(struct fd_ringbuffer * ring,gl_shader_stage type,uint32_t regid,uint32_t num,struct fd_bo ** bos,uint32_t * offsets) argument
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H A Dfd3_program.c174 (coord_regid == regid(63, 0)) ? regid(63, 0) : (coord_regid + 2);
258 reg |= A3XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
262 reg |= A3XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a3xx/
H A Dfd3_emit.c51 /* regid: base const register
57 uint32_t regid, uint32_t offset, uint32_t sizedwords,
63 debug_assert((regid % 4) == 0);
75 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
95 uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets)
100 debug_assert((regid % 4) == 0);
103 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid/2) |
365 unsigned vertex_regid = regid(63, 0);
366 unsigned instance_regid = regid(63, 0);
367 unsigned vtxcnt_regid = regid(6
56 fd3_emit_const(struct fd_ringbuffer * ring,gl_shader_stage type,uint32_t regid,uint32_t offset,uint32_t sizedwords,const uint32_t * dwords,struct pipe_resource * prsc) argument
94 fd3_emit_const_bo(struct fd_ringbuffer * ring,gl_shader_stage type,boolean write,uint32_t regid,uint32_t num,struct pipe_resource ** prscs,uint32_t * offsets) argument
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H A Dfd3_program.c213 zwcoord_regid = (coord_regid == regid(63,0)) ? regid(63,0) : (coord_regid + 2);
284 reg |= A3XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
288 reg |= A3XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
/xsrc/external/mit/MesaLib/dist/src/freedreno/computerator/
H A Da4xx.c138 A4XX_HLSQ_CL_CONTROL_0_UNK12CONSTID(regid(63, 0)) |
140 OUT_RING(ring, A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID(regid(63, 0)) |
141 A4XX_HLSQ_CL_CONTROL_1_UNK12CONSTID(regid(63, 0)));
144 OUT_RING(ring, A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID(regid(63, 0)) |
148 OUT_RING(ring, A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID(regid(63, 0)));
H A Da6xx.c168 A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
169 A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
171 OUT_RING(ring, A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
211 emit_const(struct fd_ringbuffer *ring, uint32_t regid, uint32_t sizedwords, argument
216 debug_assert((regid % 4) == 0);
221 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(regid / 4) |
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a5xx/
H A Dfd5_program.c149 if (l->var[idx].regid == v->outputs[k].regid)
156 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
193 if (l->var[idx].regid == v->outputs[k].regid)
359 zwcoord_regid = (coord_regid == regid(63,0)) ? regid(63,0) : (coord_regid + 2);
470 if (pos_regid != regid(63,0))
473 if (psize_regid != regid(63,0)) {
494 reg |= A5XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
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H A Dfd5_compute.c142 A5XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
143 A5XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/ir3/
H A Dir3_const.h43 const struct ir3_shader_variant *v, uint32_t regid,
47 const struct ir3_shader_variant *v, uint32_t regid,
52 uint32_t regid, uint32_t offset, uint32_t size,
56 emit_const_bo(ring, v, regid, offset, size, rsc->bo);
66 const struct ir3_shader_variant *v, uint32_t regid,
69 assert((regid % 4) == 0);
71 assert(regid + sizedwords <= v->constlen * 4);
474 regid(63, 0);
51 emit_const_prsc(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,uint32_t regid,uint32_t offset,uint32_t size,struct pipe_resource * buffer) argument
65 emit_const_asserts(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,uint32_t regid,uint32_t sizedwords) argument
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/freedreno/a6xx/
H A Dfd6_program.c165 if (l->var[idx].regid == v->outputs[k].regid)
172 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
209 if (l->var[idx].regid == v->outputs[k].regid)
293 if (reg == regid(63,0))
294 return regid(63,0);
299 #define VALIDREG(r) ((r) != regid(63,0))
358 smask_regid = regid(63, 0);
465 reg |= A6XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
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H A Dfd6_compute.c110 A6XX_HLSQ_CS_CNTL_0_UNK0(regid(63, 0)) |
111 A6XX_HLSQ_CS_CNTL_0_UNK1(regid(63, 0)) |
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a5xx/
H A Dfd5_emit.c53 /* regid: base const register
59 const struct ir3_shader_variant *v, uint32_t regid,
62 emit_const_asserts(ring, v, regid, sizedwords);
65 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid / 4) |
78 const struct ir3_shader_variant *v, uint32_t regid,
81 uint32_t dst_off = regid / 4;
86 emit_const_asserts(ring, v, regid, sizedwords);
98 uint32_t regid, uint32_t num, struct fd_bo **bos,
104 debug_assert((regid % 4) == 0);
107 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(regid /
58 fd5_emit_const_user(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,uint32_t regid,uint32_t sizedwords,const uint32_t * dwords) argument
77 fd5_emit_const_bo(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,uint32_t regid,uint32_t offset,uint32_t sizedwords,struct fd_bo * bo) argument
97 fd5_emit_const_ptrs(struct fd_ringbuffer * ring,gl_shader_stage type,uint32_t regid,uint32_t num,struct fd_bo ** bos,uint32_t * offsets) argument
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