| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_uvd_v3_1.c | 51 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));
54 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));
57 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0));
|
| radeon_uvd_v2_2.c | 50 radeon_ring_write(ring, PACKET0(UVD_CONTEXT_ID, 0));
52 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
54 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
56 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
59 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
61 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
63 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
84 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_LOW, 0));
87 radeon_ring_write(ring, PACKET0(UVD_SEMA_ADDR_HIGH, 0));
90 radeon_ring_write(ring, PACKET0(UVD_SEMA_CMD, 0))
[all...] |
| radeon_uvd_v1_0.c | 92 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
94 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
96 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
99 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA0, 0));
101 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_DATA1, 0));
103 radeon_ring_write(ring, PACKET0(UVD_GPCOM_VCPU_CMD, 0));
191 tmp = PACKET0(UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
195 tmp = PACKET0(UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
199 tmp = PACKET0(UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
204 radeon_ring_write(ring, PACKET0(UVD_SEMA_TIMEOUT_STATUS, 0))
[all...] |
| radeon_r300.c | 251 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_TL, 0));
253 radeon_ring_write(ring, PACKET0(R300_RE_SCISSORS_BR, 0));
256 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
258 radeon_ring_write(ring, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
261 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
265 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
268 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
271 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
273 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
304 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0))
[all...] |
| radeon_rv515.c | 80 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0));
86 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
88 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
90 radeon_ring_write(ring, PACKET0(GB_SELECT, 0));
92 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0));
94 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0));
96 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0));
98 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
100 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
102 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0))
[all...] |
| radeon_r200.c | 110 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
118 radeon_ring_write(ring, PACKET0(0x720, 2));
125 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
|
| radeon_r420.c | 230 radeon_ring_write(ring, PACKET0(R300_CP_RESYNC_ADDR, 1));
246 radeon_ring_write(ring, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
|
| radeon_uvd.c | 758 ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0);
760 ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0);
762 ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0);
765 ib.ptr[i] = PACKET0(UVD_NO_OP, 0);
|
| radeon_r100.c | 868 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
871 radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
884 radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
886 radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
889 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
893 radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
895 radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
970 radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
972 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
1009 radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0))
[all...] |
| r300d.h | 62 #define PACKET0(reg, n) (CP_PACKET0 | \
|
| radeon_ni.c | 2066 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));
2703 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0));
2707 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
2711 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_uvd_v5_0.c | 177 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
181 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
185 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
190 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
193 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
473 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
475 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
477 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
479 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
482 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0))
[all...] |
| amdgpu_uvd_v4_2.c | 180 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
184 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
188 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
193 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
196 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
456 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
458 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
460 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
462 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
465 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0))
[all...] |
| amdgpu_uvd_v6_0.c | 492 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0);
496 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0);
500 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0);
505 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0));
508 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0));
906 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0));
908 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
910 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
912 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
915 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0))
[all...] |
| amdgpu_uvd_v7_0.c | 557 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
562 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
567 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
573 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
577 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
1170 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
1173 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1176 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1179 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1183 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0))
[all...] |
| amdgpu_vcn_v2_0.c | 1302 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1304 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1319 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1338 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.nop, 0));
1357 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.context_id, 0));
1360 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1363 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0));
1366 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.cmd, 0));
1369 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data0, 0));
1372 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.data1, 0))
[all...] |
| amdgpu_vcn_v1_0.c | 1430 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1433 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1449 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1469 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1472 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1475 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1478 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1482 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1485 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1488 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0))
[all...] |
| amdgpu_jpeg.c | 125 amdgpu_ring_write(ring, PACKET0(adev->jpeg.internal.jpeg_pitch, 0));
|
| amdgpu_vcn.c | 371 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
404 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0);
406 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0);
408 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0);
411 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0);
|
| amdgpu_uvd.c | 1075 data[0] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA0, 0);
1076 data[1] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA1, 0);
1077 data[2] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_CMD, 0);
1078 data[3] = PACKET0(offset[offset_idx] + UVD_NO_OP, 0);
|
| nvd.h | 41 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
|
| soc15d.h | 43 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
|
| vid.h | 100 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
|
| cikd.h | 218 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
|
| amdgpu_jpeg_v1_0.c | 545 .nop = PACKET0(0x81ff, 0),
|
