| /src/sys/arch/riscv/sunxi/ |
| sun20i_d1_ccu.c | 341 SUNXI_CCU_GATE(D1_CLK_BUS_DE, "bus-de", "psi",
344 SUNXI_CCU_GATE(D1_CLK_BUS_DI, "bus-di", "psi",
347 SUNXI_CCU_GATE(D1_CLK_BUS_G2D, "bus-g2d", "psi",
350 SUNXI_CCU_GATE(D1_CLK_BUS_CE, "bus-ce", "psi",
353 SUNXI_CCU_GATE(D1_CLK_BUS_VE, "bus-ve", "psi",
356 SUNXI_CCU_GATE(D1_CLK_BUS_DMA, "bus-dma", "psi",
359 SUNXI_CCU_GATE(D1_CLK_BUS_MSGBOX0, "bus-msgbox0", "psi",
361 SUNXI_CCU_GATE(D1_CLK_BUS_MSGBOX1, "bus-msgbox1", "psi",
363 SUNXI_CCU_GATE(D1_CLK_BUS_MSGBOX2, "bus-msgbox2", "psi",
366 SUNXI_CCU_GATE(D1_CLK_BUS_SPINLOCK, "bus-spinlock", "psi"
[all...] |
| /src/sys/arch/arm/sunxi/ |
| sun5i_a13_ccu.c | 114 SUNXI_CCU_GATE(A13_CLK_HOSC, "osc24m", "hosc",
212 SUNXI_CCU_GATE(A13_CLK_AHB_OTG, "ahb-otg", "ahb",
214 SUNXI_CCU_GATE(A13_CLK_AHB_EHCI, "ahb-ehci", "ahb",
216 SUNXI_CCU_GATE(A13_CLK_AHB_OHCI, "ahb-ohci", "ahb",
218 SUNXI_CCU_GATE(A13_CLK_AHB_DMA, "ahb-dma", "ahb",
220 SUNXI_CCU_GATE(A13_CLK_AHB_BIST, "ahb-bist", "ahb",
222 SUNXI_CCU_GATE(A13_CLK_AHB_MMC0, "ahb-mmc0", "ahb",
224 SUNXI_CCU_GATE(A13_CLK_AHB_MMC1, "ahb-mmc1", "ahb",
226 SUNXI_CCU_GATE(A13_CLK_AHB_MMC2, "ahb-mmc2", "ahb",
228 SUNXI_CCU_GATE(A13_CLK_AHB_NAND, "ahb-nand", "ahb"
[all...] |
| sun6i_a31_ccu.c | 206 SUNXI_CCU_GATE(A31_CLK_AHB1_DMA, "ahb1-dma", "ahb1",
208 SUNXI_CCU_GATE(A31_CLK_AHB1_MMC0, "ahb1-mmc0", "ahb1",
210 SUNXI_CCU_GATE(A31_CLK_AHB1_MMC1, "ahb1-mmc1", "ahb1",
212 SUNXI_CCU_GATE(A31_CLK_AHB1_MMC2, "ahb1-mmc2", "ahb1",
214 SUNXI_CCU_GATE(A31_CLK_AHB1_MMC3, "ahb1-mmc3", "ahb1",
216 SUNXI_CCU_GATE(A31_CLK_AHB1_EMAC, "ahb1-emac", "ahb1",
218 SUNXI_CCU_GATE(A31_CLK_AHB1_OTG, "ahb1-otg", "ahb1",
220 SUNXI_CCU_GATE(A31_CLK_AHB1_EHCI0, "ahb1-ehci0", "ahb1",
222 SUNXI_CCU_GATE(A31_CLK_AHB1_EHCI1, "ahb1-ehci1", "ahb1",
224 SUNXI_CCU_GATE(A31_CLK_AHB1_OHCI0, "ahb1-ohci0", "ahb1"
[all...] |
| sun4i_a10_ccu.c | 168 SUNXI_CCU_GATE(A10_CLK_HOSC, "osc24m", "hosc",
508 SUNXI_CCU_GATE(A10_CLK_AHB_OTG, "ahb-otg", "ahb",
510 SUNXI_CCU_GATE(A10_CLK_AHB_EHCI0, "ahb-ehci0", "ahb",
512 SUNXI_CCU_GATE(A10_CLK_AHB_OHCI0, "ahb-ohci0", "ahb",
514 SUNXI_CCU_GATE(A10_CLK_AHB_EHCI1, "ahb-ehci1", "ahb",
516 SUNXI_CCU_GATE(A10_CLK_AHB_OHCI1, "ahb-ohci1", "ahb",
518 SUNXI_CCU_GATE(A10_CLK_AHB_SS, "ahb-ss", "ahb",
520 SUNXI_CCU_GATE(A10_CLK_AHB_DMA, "ahb-dma", "ahb",
522 SUNXI_CCU_GATE(A10_CLK_AHB_BIST, "ahb-bist", "ahb",
524 SUNXI_CCU_GATE(A10_CLK_AHB_MMC0, "ahb-mmc0", "ahb"
[all...] |
| sun50i_a64_ccu.c | 431 SUNXI_CCU_GATE(A64_CLK_AC_DIG, "ac-dig", "pll_audio",
433 SUNXI_CCU_GATE(A64_CLK_AC_DIG_4X, "ac-dig-4x", "pll_audio_4x",
443 SUNXI_CCU_GATE(A64_CLK_HDMI_DDC, "hdmi-ddc", "hosc",
502 SUNXI_CCU_GATE(A64_CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1",
504 SUNXI_CCU_GATE(A64_CLK_BUS_CE, "bus-ce", "ahb1",
506 SUNXI_CCU_GATE(A64_CLK_BUS_DMA, "bus-dma", "ahb1",
508 SUNXI_CCU_GATE(A64_CLK_BUS_MMC0, "bus-mmc0", "ahb1",
510 SUNXI_CCU_GATE(A64_CLK_BUS_MMC1, "bus-mmc1", "ahb1",
512 SUNXI_CCU_GATE(A64_CLK_BUS_MMC2, "bus-mmc2", "ahb1",
514 SUNXI_CCU_GATE(A64_CLK_BUS_NAND, "bus-nand", "ahb1"
[all...] |
| sun8i_h3_ccu.c | 393 SUNXI_CCU_GATE(H3_CLK_AC_DIG, "ac_dig", "pll_audio",
403 SUNXI_CCU_GATE(H3_CLK_HDMI_DDC, "hdmi-ddc", "hosc",
413 SUNXI_CCU_GATE(H3_CLK_BUS_CE, "bus-ce", "ahb1",
415 SUNXI_CCU_GATE(H3_CLK_BUS_DMA, "bus-dma", "ahb1",
417 SUNXI_CCU_GATE(H3_CLK_BUS_MMC0, "bus-mmc0", "ahb1",
419 SUNXI_CCU_GATE(H3_CLK_BUS_MMC1, "bus-mmc1", "ahb1",
421 SUNXI_CCU_GATE(H3_CLK_BUS_MMC2, "bus-mmc2", "ahb1",
423 SUNXI_CCU_GATE(H3_CLK_BUS_EMAC, "bus-emac", "ahb2",
425 SUNXI_CCU_GATE(H3_CLK_BUS_SPI0, "bus-spi0", "ahb1",
427 SUNXI_CCU_GATE(H3_CLK_BUS_SPI1, "bus-spi1", "ahb1"
[all...] |
| sun9i_a80_usbclk.c | 94 SUNXI_CCU_GATE(CLK_BUS_HCI0, "bus-hci0", "bus", HCI_SCR, 1),
95 SUNXI_CCU_GATE(CLK_USB_OHCI0, "usb-ohci0", "hosc", HCI_SCR, 2),
96 SUNXI_CCU_GATE(CLK_BUS_HCI1, "bus-hci1", "bus", HCI_SCR, 3),
97 SUNXI_CCU_GATE(CLK_BUS_HCI2, "bus-hci2", "bus", HCI_SCR, 5),
98 SUNXI_CCU_GATE(CLK_USB_OHCI2, "usb-ohci2", "hosc", HCI_SCR, 6),
100 SUNXI_CCU_GATE(CLK_USB0_PHY, "usb0-phy", "hosc", HCI_PCR, 1),
101 SUNXI_CCU_GATE(CLK_USB1_HSIC, "usb1-hsic", "hosc", HCI_PCR, 2),
102 SUNXI_CCU_GATE(CLK_USB1_PHY, "usb1-phy", "hosc", HCI_PCR, 3),
103 SUNXI_CCU_GATE(CLK_USB2_HSIC, "usb2-hsic", "hosc", HCI_PCR, 4),
104 SUNXI_CCU_GATE(CLK_USB2_PHY, "usb2-phy", "hosc", HCI_PCR, 5)
[all...] |
| sun8i_a83t_ccu.c | 266 SUNXI_CCU_GATE(A83T_CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1",
268 SUNXI_CCU_GATE(A83T_CLK_BUS_SS, "bus-ss", "ahb1",
270 SUNXI_CCU_GATE(A83T_CLK_BUS_DMA, "bus-dma", "ahb1",
272 SUNXI_CCU_GATE(A83T_CLK_BUS_MMC0, "bus-mmc0", "ahb1",
274 SUNXI_CCU_GATE(A83T_CLK_BUS_MMC1, "bus-mmc1", "ahb1",
276 SUNXI_CCU_GATE(A83T_CLK_BUS_MMC2, "bus-mmc2", "ahb1",
278 SUNXI_CCU_GATE(A83T_CLK_BUS_NAND, "bus-nand", "ahb1",
280 SUNXI_CCU_GATE(A83T_CLK_BUS_DRAM, "bus-dram", "ahb1",
282 SUNXI_CCU_GATE(A83T_CLK_BUS_EMAC, "bus-emac", "ahb2",
284 SUNXI_CCU_GATE(A83T_CLK_BUS_HSTIMER, "bus-hstimer", "ahb1"
[all...] |
| sun8i_v3s_ccu.c | 313 SUNXI_CCU_GATE(V3S_CLK_AC_DIG, "ac_dig", "pll_audio",
323 SUNXI_CCU_GATE(V3S_CLK_BUS_DMA, "bus-dma", "ahb1",
325 SUNXI_CCU_GATE(V3S_CLK_BUS_MMC0, "bus-mmc0", "ahb1",
327 SUNXI_CCU_GATE(V3S_CLK_BUS_MMC1, "bus-mmc1", "ahb1",
329 SUNXI_CCU_GATE(V3S_CLK_BUS_MMC2, "bus-mmc2", "ahb1",
331 SUNXI_CCU_GATE(V3S_CLK_BUS_EMAC, "bus-emac", "ahb2",
333 SUNXI_CCU_GATE(V3S_CLK_BUS_SPI, "bus-spi", "ahb1",
335 SUNXI_CCU_GATE(V3S_CLK_BUS_OTG, "bus-otg", "ahb1",
337 SUNXI_CCU_GATE(V3S_CLK_BUS_EHCI, "bus-ehci", "ahb1",
339 SUNXI_CCU_GATE(V3S_CLK_BUS_OHCI, "bus-ohci", "ahb1"
[all...] |
| sun50i_h6_ccu.c | 283 SUNXI_CCU_GATE(H6_CLK_BUS_MMC0, "bus-mmc0", "mmc0",
285 SUNXI_CCU_GATE(H6_CLK_BUS_MMC1, "bus-mmc1", "mmc1",
287 SUNXI_CCU_GATE(H6_CLK_BUS_MMC2, "bus-mmc2", "mmc2",
290 SUNXI_CCU_GATE(H6_CLK_BUS_UART0, "bus-uart0", "apb2",
292 SUNXI_CCU_GATE(H6_CLK_BUS_UART1, "bus-uart1", "apb2",
294 SUNXI_CCU_GATE(H6_CLK_BUS_UART2, "bus-uart2", "apb2",
296 SUNXI_CCU_GATE(H6_CLK_BUS_UART3, "bus-uart3", "apb2",
299 SUNXI_CCU_GATE(H6_CLK_BUS_I2C0, "bus-i2c0", "apb2",
301 SUNXI_CCU_GATE(H6_CLK_BUS_I2C1, "bus-i2c1", "apb2",
303 SUNXI_CCU_GATE(H6_CLK_BUS_I2C2, "bus-i2c2", "apb2"
[all...] |
| sun9i_a80_ccu.c | 308 SUNXI_CCU_GATE(A80_CLK_BUS_FD, "ahb0-fd", "ahb0",
310 SUNXI_CCU_GATE(A80_CLK_BUS_GPU_CTRL, "ahb0-gpu-ctrl", "ahb0",
312 SUNXI_CCU_GATE(A80_CLK_BUS_SS, "ahb0-ss", "ahb0",
314 SUNXI_CCU_GATE(A80_CLK_BUS_MMC, "ahb0-mmc", "ahb0",
316 SUNXI_CCU_GATE(A80_CLK_BUS_NAND1, "ahb0-nand1", "ahb0",
318 SUNXI_CCU_GATE(A80_CLK_BUS_NAND0, "ahb0-nand0", "ahb0",
320 SUNXI_CCU_GATE(A80_CLK_BUS_TS, "ahb0-ts", "ahb0",
322 SUNXI_CCU_GATE(A80_CLK_BUS_SPI0, "ahb0-spi0", "ahb0",
324 SUNXI_CCU_GATE(A80_CLK_BUS_SPI1, "ahb0-spi1", "ahb0",
326 SUNXI_CCU_GATE(A80_CLK_BUS_SPI2, "ahb0-spi2", "ahb0"
[all...] |
| sun50i_h6_r_ccu.c | 101 SUNXI_CCU_GATE(H6_R_CLK_APB1_TIMER, "apb1-timer", "apb1", 0x11c, 0),
102 SUNXI_CCU_GATE(H6_R_CLK_APB1_TWD, "apb1-twd", "apb1", 0x12c, 0),
103 SUNXI_CCU_GATE(H6_R_CLK_APB1_PWM, "apb1-pwm", "apb1", 0x13c, 0),
104 SUNXI_CCU_GATE(H6_R_CLK_APB2_UART, "apb2-uart", "apb2", 0x18c, 0),
105 SUNXI_CCU_GATE(H6_R_CLK_APB2_I2C, "apb2-i2c", "apb2", 0x19c, 0),
106 SUNXI_CCU_GATE(H6_R_CLK_APB2_RSB, "apb2-rsb", "apb2", 0x1bc, 0),
107 SUNXI_CCU_GATE(H6_R_CLK_APB1_IR, "apb1-ir", "apb1", 0x1cc, 0),
108 SUNXI_CCU_GATE(H6_R_CLK_APB1_W1, "apb1-w1", "apb1", 0x1ec, 0),
|
| sun50i_a64_r_ccu.c | 89 SUNXI_CCU_GATE(A64_R_CLK_APB0_PIO, "apb0-pio", "apb0",
91 SUNXI_CCU_GATE(A64_R_CLK_APB0_IR, "apb0-ir", "apb0",
93 SUNXI_CCU_GATE(A64_R_CLK_APB0_TIMER, "apb0-timer", "apb0",
95 SUNXI_CCU_GATE(A64_R_CLK_APB0_RSB, "apb0-rsb", "apb0",
97 SUNXI_CCU_GATE(A64_R_CLK_APB0_UART, "apb0-uart", "apb0",
99 SUNXI_CCU_GATE(A64_R_CLK_APB0_I2C, "apb0-i2c", "apb0",
101 SUNXI_CCU_GATE(A64_R_CLK_APB0_TWD, "apb0-twd", "apb0",
|
| sun8i_h3_r_ccu.c | 86 SUNXI_CCU_GATE(H3_R_CLK_APB0_PIO, "apb0-pio", "apb0",
88 SUNXI_CCU_GATE(H3_R_CLK_APB0_IR, "apb0-ir", "apb0",
90 SUNXI_CCU_GATE(H3_R_CLK_APB0_TIMER, "apb0-timer", "apb0",
92 SUNXI_CCU_GATE(H3_R_CLK_APB0_UART, "apb0-uart", "apb0",
94 SUNXI_CCU_GATE(H3_R_CLK_APB0_I2C, "apb0-i2c", "apb0",
|
| sunxi_ccu_gate.c | 1 /* $NetBSD: sunxi_ccu_gate.c,v 1.2 2017/06/29 17:06:21 jmcneill Exp $ */
30 __KERNEL_RCSID(0, "$NetBSD: sunxi_ccu_gate.c,v 1.2 2017/06/29 17:06:21 jmcneill Exp $");
43 struct sunxi_ccu_gate *gate = &clk->u.gate;
46 KASSERT(clk->type == SUNXI_CCU_GATE);
61 struct sunxi_ccu_gate *gate = &clk->u.gate;
63 KASSERT(clk->type == SUNXI_CCU_GATE);
|
| sun9i_a80_mmcclk.c | 63 SUNXI_CCU_GATE(0, "mmc0_config", "ahb", SDC_COMM(0), 16),
64 SUNXI_CCU_GATE(1, "mmc1_config", "ahb", SDC_COMM(1), 16),
65 SUNXI_CCU_GATE(2, "mmc2_config", "ahb", SDC_COMM(2), 16),
66 SUNXI_CCU_GATE(3, "mmc3_config", "ahb", SDC_COMM(3), 16),
|
| sunxi_de2_ccu.c | 63 SUNXI_CCU_GATE(DE2_CLK_BUS_MIXER0, "bus-mixer0", "bus", 0x04, 0),
64 SUNXI_CCU_GATE(DE2_CLK_BUS_MIXER1, "bus-mixer1", "bus", 0x04, 1),
65 SUNXI_CCU_GATE(DE2_CLK_BUS_WB, "bus-wb", "bus", 0x04, 2),
74 SUNXI_CCU_GATE(DE2_CLK_MIXER0, "mixer0", "mixer0-div", 0x00, 0),
75 SUNXI_CCU_GATE(DE2_CLK_MIXER1, "mixer1", "mixer1-div", 0x00, 1),
76 SUNXI_CCU_GATE(DE2_CLK_WB, "wb", "wb-div", 0x00, 2),
|
| sunxi_ccu.h | 59 SUNXI_CCU_GATE,
70 struct sunxi_ccu_gate { struct
81 #define SUNXI_CCU_GATE(_id, _name, _pname, _reg, _bit) \
83 .type = SUNXI_CCU_GATE, \
450 struct sunxi_ccu_gate gate;
|
| sunxi_ccu.c | 354 case SUNXI_CCU_GATE: type = "gate"; break;
|
