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    Searched refs:sc_wdcdev (Results 1 - 25 of 66) sorted by relevancy

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  /src/sys/dev/pci/
viaide.c 432 sc->sc_wdcdev.sc_atac.atac_dev = self;
521 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
534 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
535 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
548 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
555 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
558 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
565 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
568 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
575 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5
    [all...]
artsata.c 113 sc->sc_wdcdev.sc_atac.atac_dev = self;
136 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
144 device_xname(sc->sc_wdcdev.sc_atac.atac_dev));
146 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
149 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
162 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
170 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
181 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
196 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
204 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev
    [all...]
svwsata.c 99 sc->sc_wdcdev.sc_atac.atac_dev = self;
131 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
136 sc->sc_wdcdev.cap = WDC_CAPABILITY_WIDEREGS;
138 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
139 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
141 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
142 sc->sc_wdcdev.irqack = pciide_irqack;
143 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
144 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
147 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray
    [all...]
cmdide.c 121 sc->sc_wdcdev.sc_atac.atac_dev = self;
155 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
159 sc->sc_wdcdev.sc_atac.atac_claim_hw = cmd064x_claim_hw;
160 sc->sc_wdcdev.sc_atac.atac_free_hw = cmd064x_free_hw;
164 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
178 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
213 for(uint i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
238 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
250 sc->sc_wdcdev.sc_atac.atac_dev), i);
278 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev
    [all...]
schide.c 110 sc->sc_wdcdev.sc_atac.atac_dev = self;
127 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
131 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
134 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
135 sc->sc_wdcdev.irqack = pciide_irqack;
137 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
138 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
139 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
140 sc->sc_wdcdev.sc_atac.atac_set_modes = sch_setup_channel;
141 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray
    [all...]
stpcide.c 80 sc->sc_wdcdev.sc_atac.atac_dev = self;
97 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
101 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
103 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
104 sc->sc_wdcdev.irqack = pciide_irqack;
106 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
107 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
108 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
109 sc->sc_wdcdev.sc_atac.atac_set_modes = stpc_setup_channel;
110 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray
    [all...]
pdcsata.c 216 sc->sc_wdcdev.sc_atac.atac_dev = self;
238 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
246 device_xname(sc->sc_wdcdev.sc_atac.atac_dev));
249 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
256 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
264 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
275 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
282 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
284 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16;
286 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA
    [all...]
iteide.c 90 sc->sc_wdcdev.sc_atac.atac_dev = self;
111 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cfg & IT_CFG_MASK,
117 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
122 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
125 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
126 sc->sc_wdcdev.irqack = pciide_irqack;
128 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
129 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
130 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
132 sc->sc_wdcdev.sc_atac.atac_set_modes = ite_setup_channel
    [all...]
cypide.c 83 sc->sc_wdcdev.sc_atac.atac_dev = self;
109 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
114 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
118 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
125 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
130 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
132 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
133 sc->sc_wdcdev.irqack = pciide_irqack;
135 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
136 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2
    [all...]
toshide.c 103 sc->sc_wdcdev.sc_atac.atac_dev = self;
124 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
130 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA32 | ATAC_CAP_DATA16;
131 sc->sc_wdcdev.sc_atac.atac_pio_cap = 5;
134 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
135 sc->sc_wdcdev.irqack = pciide_irqack;
136 sc->sc_wdcdev.sc_atac.atac_dma_cap = 3;
137 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
140 sc->sc_wdcdev.sc_atac.atac_set_modes = piccolo_setup_channel;
142 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray
    [all...]
geodeide.c 96 sc->sc_wdcdev.sc_atac.atac_dev = self;
111 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
116 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DMA | ATAC_CAP_UDMA;
117 sc->sc_wdcdev.irqack = pciide_irqack;
122 sc->sc_wdcdev.dma_init = geodeide_dma_init;
124 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
125 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
126 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
133 sc->sc_wdcdev.sc_atac.atac_udma_cap = 1;
135 sc->sc_wdcdev.sc_atac.atac_set_modes = geodeide_setup_channel
    [all...]
rccide.c 106 sc->sc_wdcdev.sc_atac.atac_dev = self;
123 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
127 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
130 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
131 sc->sc_wdcdev.irqack = pciide_irqack;
133 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
134 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
137 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
141 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
143 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5
    [all...]
siside.c 103 sc->sc_wdcdev.sc_atac.atac_dev = self;
234 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
247 sc->sc_wdcdev.sc_atac.atac_udma_cap =
252 sc->sc_wdcdev.sc_atac.atac_udma_cap =
256 sc->sc_wdcdev.sc_atac.atac_udma_cap =
262 sc->sc_wdcdev.sc_atac.atac_udma_cap =
269 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
272 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
278 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
283 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32
    [all...]
pciide_common.c 183 rv = wdcdetach(sc->sc_wdcdev.sc_atac.atac_dev, flags);
187 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
209 for (drive = 0; drive < sc->sc_wdcdev.wdc_maxdrives; drive++) {
236 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
248 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
273 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
279 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
300 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
309 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
319 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev
    [all...]
aceride.c 90 sc->sc_wdcdev.sc_atac.atac_dev = self;
123 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
127 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
129 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
131 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
133 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
135 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
137 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
139 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
141 sc->sc_wdcdev.irqack = pciide_irqack
    [all...]
  /src/sys/arch/arm/gemini/
obio_wdc.c 57 struct wdc_softc sc_wdcdev; member in struct:wdc_obio_softc
109 sc->sc_wdcdev.sc_atac.atac_dev = self;
110 sc->sc_wdcdev.regs = wdr = &sc->wdc_regs;
133 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16;
135 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0;
137 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanlist;
138 sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
139 sc->sc_wdcdev.wdc_maxdrives = 2;
141 sc->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
151 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_NOIRQ
    [all...]
  /src/sys/arch/evbarm/iq31244/
wdc_obio.c 53 struct wdc_softc sc_wdcdev; member in struct:wdc_obio_softc
80 sc->sc_wdcdev.sc_atac.atac_dev = self;
81 sc->sc_wdcdev.regs = wdr = &sc->wdc_regs;
104 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16;
106 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0;
108 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanlist;
109 sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
110 sc->sc_wdcdev.wdc_maxdrives = 2;
112 sc->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
128 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_NOIRQ
    [all...]
  /src/sys/arch/evbarm/tsarm/
wdc_ts.c 50 struct wdc_softc sc_wdcdev; member in struct:wdc_ts_softc
77 sc->sc_wdcdev.sc_atac.atac_dev = self;
78 sc->sc_wdcdev.regs = wdr = &sc->wdc_regs;
101 sc->sc_wdcdev.cap |= WDC_CAPABILITY_PREATA;
102 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16;
104 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0;
106 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanlist;
107 sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
108 sc->sc_wdcdev.wdc_maxdrives = 2;
110 sc->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac
    [all...]
  /src/sys/arch/prep/pnpbus/
wdc_pnpbus.c 54 struct wdc_softc sc_wdcdev; member in struct:wdc_pnpbus_softc
104 sc->sc_wdcdev.sc_atac.atac_dev = self;
105 sc->sc_wdcdev.regs = wdr = &sc->sc_wdc_regs;
129 sc->sc_wdcdev.cap |= WDC_CAPABILITY_PREATA;
130 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16;
131 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
133 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA32;
135 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0;
137 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_chanlist;
138 sc->sc_wdcdev.sc_atac.atac_nchannels = 1
    [all...]
  /src/sys/dev/isa/
wdc_isa.c 59 struct wdc_softc sc_wdcdev; member in struct:wdc_isa_softc
167 sc->sc_wdcdev.sc_atac.atac_dev = self;
168 sc->sc_wdcdev.regs = wdr = &sc->wdc_regs;
197 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
198 sc->sc_wdcdev.dma_arg = sc;
199 sc->sc_wdcdev.dma_init = wdc_isa_dma_init;
200 sc->sc_wdcdev.dma_start = wdc_isa_dma_start;
201 sc->sc_wdcdev.dma_finish = wdc_isa_dma_finish;
205 sc->sc_wdcdev.cap |= WDC_CAPABILITY_PREATA;
206 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16
    [all...]
  /src/sys/arch/i386/pnpbios/
pciide_pnpbios.c 90 sc->sc_wdcdev.sc_atac.atac_dev = self;
119 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
135 sc->sc_wdcdev.dma_arg = sc;
136 sc->sc_wdcdev.dma_init = pciide_dma_init;
137 sc->sc_wdcdev.dma_start = pciide_dma_start;
138 sc->sc_wdcdev.dma_finish = pciide_dma_finish;
139 sc->sc_wdcdev.irqack = pciide_irqack;
140 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
141 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
142 sc->sc_wdcdev.sc_atac.atac_nchannels = 1
    [all...]
  /src/sys/arch/macppc/dev/
wdc_obio.c 66 struct wdc_softc sc_wdcdev; member in struct:wdc_obio_softc
127 sc->sc_wdcdev.sc_atac.atac_dev = self;
128 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
154 sc->sc_wdcdev.regs = wdr = &sc->sc_wdc_regs;
207 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
208 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
210 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
211 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
212 sc->sc_wdcdev.sc_atac.atac_set_modes =
215 sc->sc_wdcdev.sc_atac.atac_set_modes = adjust_timing
    [all...]
  /src/sys/arch/evbppc/mpc85xx/
wdc_obio.c 53 struct wdc_softc sc_wdcdev; member in struct:wdc_obio_softc
136 sc->sc_wdcdev.sc_atac.atac_dev = self;
137 sc->sc_wdcdev.regs = wdr;
143 //sc->sc_wdcdev.cap |= WDC_CAPABILITY_NO_EXTRA_RESETS;
144 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16;
146 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0;
148 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanlist;
149 sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
150 sc->sc_wdcdev.wdc_maxdrives = 2;
152 sc->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac
    [all...]
  /src/sys/arch/amiga/dev/
wdc_buddha.c 53 struct wdc_softc sc_wdcdev; member in struct:wdc_buddha_softc
94 sc->sc_wdcdev.sc_atac.atac_dev = self;
112 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16;
113 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0;
114 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
115 sc->sc_wdcdev.sc_atac.atac_nchannels = nchannels;
116 sc->sc_wdcdev.wdc_maxdrives = 2;
118 wdc_allocate_regs(&sc->sc_wdcdev);
129 cp->ch_atac = &sc->sc_wdcdev.sc_atac;
188 nchannels = sc->sc_wdcdev.sc_atac.atac_nchannels
    [all...]
  /src/sys/arch/landisk/dev/
wdc_obio.c 49 struct wdc_softc sc_wdcdev; member in struct:wdc_obio_softc
132 sc->sc_wdcdev.sc_atac.atac_dev = self;
133 sc->sc_wdcdev.regs = wdr = &sc->sc_wdc_regs;
159 sc->sc_wdcdev.cap |= WDC_CAPABILITY_PREATA;
160 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16;
161 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0;
163 sc->sc_wdcdev.sc_atac.atac_channels = sc->sc_chanlist;
164 sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
165 sc->sc_wdcdev.wdc_maxdrives = 2;
167 sc->sc_channel.ch_atac = &sc->sc_wdcdev.sc_atac
    [all...]

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