/src/sys/external/bsd/drm2/dist/drm/radeon/ |
radeon_asic.c | 200 .set_wptr = &r100_gfx_set_wptr, 350 .set_wptr = &r100_gfx_set_wptr, 364 .set_wptr = &r100_gfx_set_wptr, 921 .set_wptr = &r600_gfx_set_wptr, 934 .set_wptr = &r600_dma_set_wptr, 1019 .set_wptr = &uvd_v1_0_set_wptr, 1222 .set_wptr = &uvd_v1_0_set_wptr, 1331 .set_wptr = &r600_gfx_set_wptr, 1344 .set_wptr = &r600_dma_set_wptr, 1646 .set_wptr = &cayman_gfx_set_wptr [all...] |
radeon.h | 1861 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); member in struct:radeon_asic_ring 2803 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
|
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
amdgpu_ring.h | 128 void (*set_wptr)(struct amdgpu_ring *ring); member in struct:amdgpu_ring_funcs 241 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
|
amdgpu_uvd_v6_0.c | 1527 .set_wptr = uvd_v6_0_ring_set_wptr, 1553 .set_wptr = uvd_v6_0_ring_set_wptr, 1582 .set_wptr = uvd_v6_0_enc_ring_set_wptr,
|
amdgpu_jpeg_v2_5.c | 583 .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
|
amdgpu_vce_v2_0.c | 616 .set_wptr = vce_v2_0_ring_set_wptr,
|
amdgpu_vce_v3_0.c | 905 .set_wptr = vce_v3_0_ring_set_wptr, 929 .set_wptr = vce_v3_0_ring_set_wptr,
|
amdgpu_jpeg_v1_0.c | 552 .set_wptr = jpeg_v1_0_decode_ring_set_wptr,
|
amdgpu_jpeg_v2_0.c | 784 .set_wptr = jpeg_v2_0_dec_ring_set_wptr,
|
amdgpu_sdma_v4_0.c | 2258 .set_wptr = sdma_v4_0_ring_set_wptr, 2294 .set_wptr = sdma_v4_0_ring_set_wptr, 2326 .set_wptr = sdma_v4_0_page_ring_set_wptr, 2358 .set_wptr = sdma_v4_0_page_ring_set_wptr,
|
amdgpu_uvd_v4_2.c | 752 .set_wptr = uvd_v4_2_ring_set_wptr,
|
amdgpu_uvd_v5_0.c | 861 .set_wptr = uvd_v5_0_ring_set_wptr,
|
amdgpu_uvd_v7_0.c | 1787 .set_wptr = uvd_v7_0_ring_set_wptr, 1820 .set_wptr = uvd_v7_0_enc_ring_set_wptr,
|
amdgpu_vcn_v1_0.c | 1884 .set_wptr = vcn_v1_0_dec_ring_set_wptr, 1918 .set_wptr = vcn_v1_0_enc_ring_set_wptr,
|
amdgpu_vcn_v2_0.c | 1716 .set_wptr = vcn_v2_0_dec_ring_set_wptr, 1747 .set_wptr = vcn_v2_0_enc_ring_set_wptr,
|
amdgpu_vcn_v2_5.c | 1490 .set_wptr = vcn_v2_5_dec_ring_set_wptr, 1590 .set_wptr = vcn_v2_5_enc_ring_set_wptr,
|
amdgpu_sdma_v2_4.c | 1148 .set_wptr = sdma_v2_4_ring_set_wptr,
|
amdgpu_si_dma.c | 731 .set_wptr = si_dma_ring_set_wptr,
|
amdgpu_vce_v4_0.c | 1083 .set_wptr = vce_v4_0_ring_set_wptr,
|
amdgpu_cik_sdma.c | 1260 .set_wptr = cik_sdma_ring_set_wptr,
|
amdgpu_gfx_v10_0.c | 5159 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 5211 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 5245 .set_wptr = gfx_v10_0_ring_set_wptr_compute,
|
amdgpu_sdma_v3_0.c | 1586 .set_wptr = sdma_v3_0_ring_set_wptr,
|
amdgpu_sdma_v5_0.c | 1597 .set_wptr = sdma_v5_0_ring_set_wptr,
|
amdgpu_gfx_v6_0.c | 3498 .set_wptr = gfx_v6_0_ring_set_wptr_gfx, 3523 .set_wptr = gfx_v6_0_ring_set_wptr_compute,
|
amdgpu_gfx_v8_0.c | 6913 .set_wptr = gfx_v8_0_ring_set_wptr_gfx, 6958 .set_wptr = gfx_v8_0_ring_set_wptr_compute, 6988 .set_wptr = gfx_v8_0_ring_set_wptr_compute,
|