Searched refs:A0_ADD (Results 1 - 23 of 23) sorted by relevance

/xsrc/external/mit/xf86-video-intel/dist/xvmc/
H A Di915_program.h54 #define A0_ADD (0x1<<24) /* dst = src0 + src1 */ macro
H A Di915_reg.h536 #define A0_ADD (0x1<<24) /* dst = src0 + src1 */ macro
H A Di915_xvmc.c292 i915_inst_arith(&pixel_shader_program->inst3[i], A0_ADD, dest,
/xsrc/external/mit/xf86-video-intel-2014/dist/xvmc/
H A Di915_program.h54 #define A0_ADD (0x1<<24) /* dst = src0 + src1 */ macro
H A Di915_reg.h536 #define A0_ADD (0x1<<24) /* dst = src0 + src1 */ macro
H A Di915_xvmc.c292 i915_inst_arith(&pixel_shader_program->inst3[i], A0_ADD, dest,
/xsrc/external/mit/xf86-video-intel-old/dist/src/xvmc/
H A Di915_program.h54 #define A0_ADD (0x1<<24) /* dst = src0 + src1 */ macro
H A Di915_xvmc.c321 i915_inst_arith(&pixel_shader_program->inst3[i], A0_ADD, dest, A0_DEST_CHANNEL_ALL,
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/i915/
H A Di915_fpc_translate.c488 emit_simple_arith(p, inst, A0_ADD, 2, fs);
900 A0_ADD,
927 A0_ADD,
H A Di915_reg.h549 #define A0_ADD (0x1<<24) /* dst = src0 + src1 */ macro
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/i915/
H A Di915_fpc_translate.c431 emit_simple_arith(p, inst, A0_ADD, 2, fs);
706 i915_emit_arith(p, A0_ADD, get_result_vector(p, &inst->Dst[0]),
724 p, A0_ADD, get_result_vector(p, &inst->Dst[0]), get_result_flags(inst),
H A Di915_reg.h522 #define A0_ADD (0x1 << 24) /* dst = src0 + src1 */ macro
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i915/
H A Di915_fragprog.c434 EMIT_2ARG_ARITH(A0_ADD);
911 A0_ADD,
925 A0_ADD,
H A Di915_reg.h421 #define A0_ADD (0x1<<24) /* dst = src0 + src1 */ macro
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i915/
H A Di915_fragprog.c434 EMIT_2ARG_ARITH(A0_ADD);
911 A0_ADD,
925 A0_ADD,
H A Di915_reg.h421 #define A0_ADD (0x1<<24) /* dst = src0 + src1 */ macro
/xsrc/external/mit/xf86-video-intel/dist/src/uxa/
H A Di915_3d.h87 #define A0_ADD (0x1<<24) /* dst = src0 + src1 */ macro
H A Di915_reg.h536 #define A0_ADD (0x1<<24) /* dst = src0 + src1 */ macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/uxa/
H A Di915_3d.h87 #define A0_ADD (0x1<<24) /* dst = src0 + src1 */ macro
H A Di915_reg.h536 #define A0_ADD (0x1<<24) /* dst = src0 + src1 */ macro
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen3_render.h539 #define A0_ADD (0x1<<24) /* dst = src0 + src1 */ macro
934 #define A0_ADD (0x1<<24) /* dst = src0 + src1 */ macro
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen3_render.h539 #define A0_ADD (0x1<<24) /* dst = src0 + src1 */ macro
934 #define A0_ADD (0x1<<24) /* dst = src0 + src1 */ macro
/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di915_reg.h558 #define A0_ADD (0x1<<24) /* dst = src0 + src1 */ macro

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