Searched refs:INTEL_MASK (Results 1 - 25 of 26) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A Dbrw_defines.h37 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low)) macro
46 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
261 #define BRW_SURFACE_FORMAT_MASK INTEL_MASK(26, 18)
267 #define BRW_SURFACE_TYPE_MASK INTEL_MASK(31, 29)
288 #define GEN8_SURFACE_MOCS_MASK INTEL_MASK(30, 24)
290 #define GEN8_SURFACE_QPITCH_MASK INTEL_MASK(14, 0)
294 #define BRW_SURFACE_HEIGHT_MASK INTEL_MASK(31, 19)
296 #define BRW_SURFACE_WIDTH_MASK INTEL_MASK(18, 6)
298 #define BRW_SURFACE_LOD_MASK INTEL_MASK(5, 2)
300 #define GEN7_SURFACE_HEIGHT_MASK INTEL_MASK(2
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/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A Dbrw_defines.h37 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low)) macro
46 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
261 #define BRW_SURFACE_FORMAT_MASK INTEL_MASK(26, 18)
267 #define BRW_SURFACE_TYPE_MASK INTEL_MASK(31, 29)
288 #define GFX8_SURFACE_MOCS_MASK INTEL_MASK(30, 24)
290 #define GFX8_SURFACE_QPITCH_MASK INTEL_MASK(14, 0)
294 #define BRW_SURFACE_HEIGHT_MASK INTEL_MASK(31, 19)
296 #define BRW_SURFACE_WIDTH_MASK INTEL_MASK(18, 6)
298 #define BRW_SURFACE_LOD_MASK INTEL_MASK(5, 2)
300 #define GFX7_SURFACE_HEIGHT_MASK INTEL_MASK(2
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/xsrc/external/mit/MesaLib/dist/src/intel/perf/
H A Dintel_perf_regs.h27 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low)) macro
32 #define GFX7_RPSTAT1_CURR_GT_FREQ_MASK INTEL_MASK(13, 7)
34 #define GFX7_RPSTAT1_PREV_GT_FREQ_MASK INTEL_MASK(6, 0)
38 #define GFX9_RPSTAT0_CURR_GT_FREQ_MASK INTEL_MASK(31, 23)
40 #define GFX9_RPSTAT0_PREV_GT_FREQ_MASK INTEL_MASK(8, 0)
/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dbrw_nir.h180 #define BRW_NIR_FRAG_OUTPUT_INDEX_MASK INTEL_MASK(0, 0)
182 #define BRW_NIR_FRAG_OUTPUT_LOCATION_MASK INTEL_MASK(31, 1)
H A Dbrw_eu_defines.h40 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low)) macro
52 assert((fieldval & ~INTEL_MASK(high, low)) == 0); \
53 fieldval & INTEL_MASK(high, low); \
56 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
H A Dbrw_vec4_generator.cpp756 const int mask = ivb ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
1076 brw_imm_ud(ivb ? INTEL_MASK(15, 12) : INTEL_MASK(16, 13)));
H A Dbrw_fs_nir.cpp2611 brw_imm_ud(INTEL_MASK(16, 13)));
2617 brw_imm_ud(INTEL_MASK(30, 24)));
H A Dbrw_fs.cpp7415 INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_nir.h192 #define BRW_NIR_FRAG_OUTPUT_INDEX_MASK INTEL_MASK(0, 0)
194 #define BRW_NIR_FRAG_OUTPUT_LOCATION_MASK INTEL_MASK(31, 1)
H A Dbrw_eu_defines.h43 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low)) macro
55 assert((fieldval & ~INTEL_MASK(high, low)) == 0); \
56 fieldval & INTEL_MASK(high, low); \
59 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
H A Dbrw_vec4_generator.cpp755 const int mask = ivb ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
1075 brw_imm_ud(ivb ? INTEL_MASK(15, 12) : INTEL_MASK(16, 13)));
H A Dbrw_fs_reg_allocate.cpp1035 brw_imm_ud(INTEL_MASK(31, 10)));
H A Dbrw_fs_generator.cpp1597 brw_imm_ud(INTEL_MASK(3, 0)));
1606 brw_imm_ud(INTEL_MASK(31, 10)));
H A Dbrw_fs.cpp1697 brw_imm_ud(INTEL_MASK(31, 6)));
4890 brw_imm_ud(~INTEL_MASK(14, 11)));
5268 brw_imm_ud(INTEL_MASK(31, 5)));
5289 brw_imm_ud(INTEL_MASK(31, 5)));
9015 devinfo->ver >= 11 ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17);
H A Dbrw_fs_nir.cpp2868 brw_imm_ud(INTEL_MASK(30, 24)));
2876 brw_imm_ud(INTEL_MASK(16, 13)));
3831 brw_imm_ud(INTEL_MASK(7, 0)));
H A Dbrw_eu_emit.c2782 ((ex_desc.ud | ex_desc_imm) & INTEL_MASK(15, 12)) == 0)) {
/xsrc/external/mit/xf86-video-intel/dist/src/sna/
H A Dgen8_render.h4 #define INTEL_MASK(high, low) (((1 << ((high) - (low) + 1)) - 1) << (low)) macro
243 # define WM_DS_STENCIL_TEST_MASK_MASK INTEL_MASK(31, 24)
245 # define WM_DS_STENCIL_WRITE_MASK_MASK INTEL_MASK(23, 16)
247 # define WM_DS_BF_STENCIL_TEST_MASK_MASK INTEL_MASK(15, 8)
249 # define WM_DS_BF_STENCIL_WRITE_MASK_MASK INTEL_MASK(7, 0)
257 # define WM_DS_STENCIL_TEST_MASK_MASK INTEL_MASK(31, 24)
259 # define WM_DS_STENCIL_WRITE_MASK_MASK INTEL_MASK(23, 16)
261 # define WM_DS_BF_STENCIL_TEST_MASK_MASK INTEL_MASK(15, 8)
263 # define WM_DS_BF_STENCIL_WRITE_MASK_MASK INTEL_MASK(7, 0)
H A Dgen9_render.h4 #define INTEL_MASK(high, low) (((1 << ((high) - (low) + 1)) - 1) << (low)) macro
249 # define WM_DS_STENCIL_TEST_MASK_MASK INTEL_MASK(31, 24)
251 # define WM_DS_STENCIL_WRITE_MASK_MASK INTEL_MASK(23, 16)
253 # define WM_DS_BF_STENCIL_TEST_MASK_MASK INTEL_MASK(15, 8)
255 # define WM_DS_BF_STENCIL_WRITE_MASK_MASK INTEL_MASK(7, 0)
263 # define WM_DS_STENCIL_TEST_MASK_MASK INTEL_MASK(31, 24)
265 # define WM_DS_STENCIL_WRITE_MASK_MASK INTEL_MASK(23, 16)
267 # define WM_DS_BF_STENCIL_TEST_MASK_MASK INTEL_MASK(15, 8)
269 # define WM_DS_BF_STENCIL_WRITE_MASK_MASK INTEL_MASK(7, 0)
H A Dgen6_render.h1507 #define GEN6_SURFACE_FORMAT_MASK INTEL_MASK(26, 18)
H A Dgen7_render.h4 #define INTEL_MASK(high, low) (((1 << ((high) - (low) + 1)) - 1) << (low)) macro
H A Dgen5_render.h2138 #define GEN5_SURFACE_FORMAT_MASK INTEL_MASK(26, 18)
/xsrc/external/mit/xf86-video-intel-2014/dist/src/sna/
H A Dgen8_render.h4 #define INTEL_MASK(high, low) (((1 << ((high) - (low) + 1)) - 1) << (low)) macro
243 # define WM_DS_STENCIL_TEST_MASK_MASK INTEL_MASK(31, 24)
245 # define WM_DS_STENCIL_WRITE_MASK_MASK INTEL_MASK(23, 16)
247 # define WM_DS_BF_STENCIL_TEST_MASK_MASK INTEL_MASK(15, 8)
249 # define WM_DS_BF_STENCIL_WRITE_MASK_MASK INTEL_MASK(7, 0)
257 # define WM_DS_STENCIL_TEST_MASK_MASK INTEL_MASK(31, 24)
259 # define WM_DS_STENCIL_WRITE_MASK_MASK INTEL_MASK(23, 16)
261 # define WM_DS_BF_STENCIL_TEST_MASK_MASK INTEL_MASK(15, 8)
263 # define WM_DS_BF_STENCIL_WRITE_MASK_MASK INTEL_MASK(7, 0)
H A Dgen6_render.h1507 #define GEN6_SURFACE_FORMAT_MASK INTEL_MASK(26, 18)
H A Dgen7_render.h4 #define INTEL_MASK(high, low) (((1 << ((high) - (low) + 1)) - 1) << (low)) macro
H A Dgen5_render.h2138 #define GEN5_SURFACE_FORMAT_MASK INTEL_MASK(26, 18)

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