| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/iris/ |
| H A D | iris_defines.h | 46 #define MI_PREDICATE_SRC0 0x2400 macro
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| H A D | iris_query.c | 966 ice->vtbl.load_register_mem64(batch, MI_PREDICATE_SRC0, bo,
1036 ice->vtbl.load_register_reg64(batch, MI_PREDICATE_SRC0, CS_GPR(0));
1041 ice->vtbl.load_register_mem64(batch, MI_PREDICATE_SRC0, bo,
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/crocus/ |
| H A D | crocus_defines.h | 46 #define MI_PREDICATE_SRC0 0x2400 macro
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| H A D | crocus_query.c | 842 screen->vtbl.load_register_mem64(batch, MI_PREDICATE_SRC0, bo,
889 mi_store(&b, mi_reg64(MI_PREDICATE_SRC0), result);
965 screen->vtbl.load_register_mem32(batch, MI_PREDICATE_SRC0,
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| H A D | crocus_state.c | 7898 mi_store(&b, mi_reg64(MI_PREDICATE_SRC0), pred);
7914 * to MI_PREDICATE_SRC0.
7916 crocus_load_register_mem32(batch, MI_PREDICATE_SRC0,
7918 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
7919 crocus_load_register_imm32(batch, MI_PREDICATE_SRC0 + 4, 0);
8202 _crocus_emit_lri(batch, MI_PREDICATE_SRC0 + 4, 0);
8206 crocus_load_register_mem32(batch, MI_PREDICATE_SRC0, bo, grid_size->offset + 0);
8216 crocus_load_register_mem32(batch, MI_PREDICATE_SRC0, bo, grid_size->offset + 4);
8226 crocus_load_register_mem32(batch, MI_PREDICATE_SRC0, bo, grid_size->offset + 8);
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/iris/ |
| H A D | iris_defines.h | 46 #define MI_PREDICATE_SRC0 0x2400 macro
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| H A D | iris_state.c | 6765 * to MI_PREDICATE_SRC0.
6767 iris_load_register_mem32(batch, MI_PREDICATE_SRC0,
6769 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
6770 iris_load_register_imm32(batch, MI_PREDICATE_SRC0 + 4, 0);
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| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/ |
| H A D | brw_conditional_render.c | 69 brw_load_register_reg64(brw, MI_PREDICATE_SRC0, HSW_CS_GPR(0));
90 brw_load_register_mem64(brw, MI_PREDICATE_SRC0, query->bo, 0 /* offset */);
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| H A D | hsw_queryobj.c | 392 brw_load_register_mem64(brw, MI_PREDICATE_SRC0, query_bo,
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| H A D | brw_draw.c | 1160 * MI_PREDICATE_SRC0.
1162 brw_load_register_mem(brw, MI_PREDICATE_SRC0,
1165 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
1166 brw_load_register_imm32(brw, MI_PREDICATE_SRC0 + 4, 0);
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| H A D | brw_defines.h | 1588 #define MI_PREDICATE_SRC0 0x2400 macro
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| H A D | genX_state_upload.c | 4493 #define MI_PREDICATE_SRC0 0x2400 macro
4508 emit_lri(brw, MI_PREDICATE_SRC0 + 4, 0);
4513 emit_lrm(brw, MI_PREDICATE_SRC0, ro_bo(bo, indirect_offset + 0));
4523 emit_lrm(brw, MI_PREDICATE_SRC0, ro_bo(bo, indirect_offset + 4));
4533 emit_lrm(brw, MI_PREDICATE_SRC0, ro_bo(bo, indirect_offset + 8));
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| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/ |
| H A D | brw_conditional_render.c | 68 brw_load_register_reg64(brw, MI_PREDICATE_SRC0, HSW_CS_GPR(0));
89 brw_load_register_mem64(brw, MI_PREDICATE_SRC0, query->bo, 0 /* offset */);
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| H A D | hsw_queryobj.c | 390 brw_load_register_mem64(brw, MI_PREDICATE_SRC0, query_bo,
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| H A D | brw_draw.c | 1198 * MI_PREDICATE_SRC0.
1200 brw_load_register_mem(brw, MI_PREDICATE_SRC0,
1203 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
1204 brw_load_register_imm32(brw, MI_PREDICATE_SRC0 + 4, 0);
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| H A D | brw_defines.h | 1585 #define MI_PREDICATE_SRC0 0x2400 macro
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| H A D | genX_state_upload.c | 4422 #define MI_PREDICATE_SRC0 0x2400 macro
4437 emit_lri(brw, MI_PREDICATE_SRC0 + 4, 0);
4442 emit_lrm(brw, MI_PREDICATE_SRC0, ro_bo(bo, indirect_offset + 0));
4452 emit_lrm(brw, MI_PREDICATE_SRC0, ro_bo(bo, indirect_offset + 4));
4462 emit_lrm(brw, MI_PREDICATE_SRC0, ro_bo(bo, indirect_offset + 8));
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| /xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/ |
| H A D | genX_cmd_buffer.c | 496 #define MI_PREDICATE_SRC0 0x2400 macro
593 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0),
605 gen_mi_inot(&b, gen_mi_reg64(MI_PREDICATE_SRC0)));
619 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0),
680 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0), fast_clear_type_mem);
3118 * MI_PREDICATE_SRC0.
3120 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0),
3179 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0), pred);
3671 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0), size_x);
3680 gen_mi_store(&b, gen_mi_reg32(MI_PREDICATE_SRC0), size_
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/intel/vulkan/ |
| H A D | genX_cmd_buffer.c | 763 #define MI_PREDICATE_SRC0 0x2400 macro
843 mi_store(&b, mi_reg64(MI_PREDICATE_SRC0), compression_state);
854 mi_inot(&b, mi_reg64(MI_PREDICATE_SRC0)));
868 mi_store(&b, mi_reg64(MI_PREDICATE_SRC0), mi_value_ref(&b, pred));
928 mi_store(&b, mi_reg64(MI_PREDICATE_SRC0), fast_clear_type_mem);
4406 * MI_PREDICATE_SRC0.
4408 mi_store(b, mi_reg64(MI_PREDICATE_SRC0), mi_mem32(count_address));
4463 mi_store(b, mi_reg64(MI_PREDICATE_SRC0), pred);
5065 mi_store(&b, mi_reg64(MI_PREDICATE_SRC0), size_x);
5074 mi_store(&b, mi_reg32(MI_PREDICATE_SRC0), size_
[all...] |
| H A D | genX_query.c | 1282 #define MI_PREDICATE_SRC0 0x2400 macro
1300 mi_store(b, mi_reg64(MI_PREDICATE_SRC0), mi_mem64(poll_addr));
|