Searched refs:ngg (Results 1 - 25 of 27) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/amd/common/
H A Dac_shader_util.h105 void ac_compute_late_alloc(const struct radeon_info *info, bool ngg, bool ngg_culling,
H A Dac_shader_util.c450 void ac_compute_late_alloc(const struct radeon_info *info, bool ngg, bool ngg_culling, argument
467 if (ngg && info->family == CHIP_NAVI14)
480 if (info->chip_class == GFX10 && ngg)
510 if (ngg) /* GS */
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_state_shaders.c45 void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es, argument
69 if (ngg)
73 if (si_get_wave_size(sel->screen, sel->info.stage, ngg, es) == 32)
1006 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
1008 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
1010 shader->ctx_reg.ngg.vgt_primitiveid_en);
1012 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
1014 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
1017 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
1019 shader->ctx_reg.ngg
1116 si_get_vs_out_cntl(const struct si_shader_selector * sel,const struct si_shader * shader,bool ngg) argument
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H A Dsi_build_pm4.h285 enum si_has_gs has_gs, enum si_has_ngg ngg,
300 if (ngg || has_gs) {
322 if (ngg || has_gs) {
284 si_get_user_data_base(enum chip_class chip_class,enum si_has_tess has_tess,enum si_has_gs has_gs,enum si_has_ngg ngg,enum pipe_shader_type shader) argument
H A Dsi_shader.h750 uint8_t ngg : 1; /* gfx10+ */ member in struct:si_vgt_stages_key::__anon396a29301408
756 uint8_t ngg : 1;
806 } ngg; member in struct:si_shader
853 } ngg; member in union:si_shader::__anon396a2930160a
H A Dsi_pipe.h1103 bool ngg : 1; member in struct:si_context
1956 gl_shader_stage stage, bool ngg, bool es)
1962 else if ((stage == MESA_SHADER_VERTEX && es && !ngg) ||
1963 (stage == MESA_SHADER_TESS_EVAL && es && !ngg) ||
1964 (stage == MESA_SHADER_GEOMETRY && !ngg)) /* legacy GS only supports Wave64 */
1981 [sctx->ngg];
1985 [sctx->ngg];
1955 si_get_wave_size(struct si_screen * sscreen,gl_shader_stage stage,bool ngg,bool es) argument
H A Dsi_descriptors.c2015 sctx->ngg ? NGG_ON : NGG_OFF,
2022 sctx->ngg ? NGG_ON : NGG_OFF,
2038 sctx->shader.tes.key.as_ngg = sctx->ngg;
2039 sctx->shader.gs.key.as_ngg = sctx->ngg;
2042 sctx->shader.tes.key.as_ngg = sctx->ngg;
2047 sctx->shader.vs.key.as_ngg = sctx->ngg;
2048 sctx->shader.gs.key.as_ngg = sctx->ngg;
2052 sctx->shader.vs.key.as_ngg = sctx->ngg;
2686 sctx->ngg, PIPE_SHADER_VERTEX));
H A Dsi_state.h557 void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
H A Dgfx10_shader_ngg.c2152 shader->ngg.hw_max_esverts = max_esverts;
2153 shader->ngg.max_gsprims = max_gsprims;
2154 shader->ngg.max_out_verts = max_out_vertices;
2155 shader->ngg.prim_amp_factor = prim_amp_factor;
2156 shader->ngg.max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
2161 shader->ngg.ngg_emit_size = max_gsprims * gsprim_lds_size;
2163 assert(shader->ngg.hw_max_esverts >= min_esverts); /* HW limitation */
2168 shader->ngg.hw_max_esverts >= min_esverts;
H A Dsi_gfx_cs.c385 if (ctx->screen->info.has_vgt_flush_ngg_legacy_bug && !ctx->ngg)
H A Dsi_pipe.c555 sctx->ngg = sscreen->use_ngg;
H A Dsi_shader.c799 sym->size = shader->ngg.ngg_emit_size * 4;
H A Dsi_state_draw.cpp237 key.index |= si_get_vs_inline(sctx, HAS_TESS, HAS_GS)->current->ctx_reg.ngg.vgt_stages.index;
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A Daco_instruction_selection_setup.cpp839 bool ngg = args->shader_info->is_ngg && args->options->chip_class >= GFX10; local in function:aco::setup_isel_context
841 if (sw_stage == SWStage::VS && args->shader_info->vs.as_es && !ngg)
843 else if (sw_stage == SWStage::VS && !args->shader_info->vs.as_ls && !ngg)
845 else if (sw_stage == SWStage::VS && ngg)
855 else if (sw_stage == SWStage::VS_GS && gfx9_plus && !ngg)
857 else if (sw_stage == SWStage::VS_GS && ngg)
865 else if (sw_stage == SWStage::TES && !args->shader_info->tes.as_es && !ngg)
867 else if (sw_stage == SWStage::TES && !args->shader_info->tes.as_es && ngg)
869 else if (sw_stage == SWStage::TES && args->shader_info->tes.as_es && !ngg)
871 else if (sw_stage == SWStage::TES_GS && gfx9_plus && !ngg)
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/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D20.2.4.rst112 - radeonsi/gfx10: flush gfx cs on ngg -> legacy transition
H A D21.1.4.rst132 - radeonsi: disable ngg culling on llvm < 12
H A D20.3.0.rst3970 - radeonsi/gfx10: flush gfx cs on ngg -\> legacy transition
4518 - aco/ngg: Refactor gs_alloc_req in preparation for NGG GS.
4519 - aco/ngg: Refactor ngg_emit_prim_export in preparation for NGG GS.
4520 - aco/ngg: Make primitive export packing less prone to error.
4521 - aco/ngg: Clean up and reorganize NGG VS/TES code.
4522 - aco/ngg: Allow NGG GS to store ES outputs.
4523 - aco/ngg: Allow NGG GS to load per-vertex GS inputs.
4524 - aco/ngg: Allow NGG GS to create VS exports.
4525 - aco/ngg: Setup NGG GS.
4526 - aco/ngg
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H A D19.2.0.rst337 - radeonsi/gfx10: remove incorrect ngg/pos_writes_edgeflag variables
H A D20.1.0.rst3377 - radeonsi/ngg: add VGT_FLUSH when enabling fast launch
4222 - aco/ngg: Add new stage for hw_ngg_gs.
4223 - aco/ngg: Initialize exec mask for NGG VS and TES.
4224 - aco/ngg: Fix exports for NGG VS and TES.
4225 - aco/ngg: Setup NGG VS and TES stages.
4226 - aco/ngg: Implement NGG VS and TES.
4227 - aco/ngg: Schedule position exports of NGG VS/TES.
4228 - aco/ngg: Run GS_ALLOC_REQ on priority 3 for NGG VS and TES.
H A D21.3.0.rst2609 - radeonsi: move as_ls/es/ngg setting out of si_shader_selector_key
2720 - radeonsi: strenthen the ngg->legacy hw workaround, fix fast launch hangs too
3606 - radv: move ngg culling determination earlier
3922 - radv: move ngg early prim export determination earlier
3923 - move: move ngg lds bytes determination earlier
3924 - radv: move ngg passthrough determination earlier
3926 - radv: constify radv_shader_info for radv_lower_{io_to_mem,ngg}()
4146 - ac/nir/ngg: Delete unused struct.
H A D21.0.0.rst2604 - radeonsi/gfx10: flush gfx cs on ngg -\> legacy transition
2708 - radv/llvm,aco/ngg: fix large shift exponent in ngg_gs_vertex_lds_addr
2710 - aco/ngg: fix division-by-zero in assertion
H A D19.3.0.rst2336 - radeonsi/gfx10: remove incorrect ngg/pos_writes_edgeflag variables
H A D20.0.0.rst2716 - radeonsi/ngg: add VGT_FLUSH when enabling fast launch
H A D20.2.0.rst3724 - radeonsi/ngg: try GS multi-cycling mode if default mode failed
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_pipeline.c1990 nir_shader **nir, struct radv_shader_info *infos, struct gfx10_ngg_info *ngg)
2188 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
2190 ngg->hw_max_esverts = max_esverts;
2192 ngg->max_gsprims = max_gsprims;
2193 ngg->max_out_verts = max_out_vertices;
2194 ngg->prim_amp_factor = prim_amp_factor;
2195 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
2196 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
2197 ngg->enable_vertex_grouping = true;
2200 ngg
1989 gfx10_get_ngg_info(const struct radv_pipeline_key * key,struct radv_pipeline * pipeline,nir_shader ** nir,struct radv_shader_info * infos,struct gfx10_ngg_info * ngg) argument
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