Searched refs:ra_class_add_reg (Results 1 - 20 of 20) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/util/
H A Dregister_allocate_test.cpp98 ra_class_add_reg(reg32low, vreg);
107 ra_class_add_reg(reg64low, vreg);
116 ra_class_add_reg(reg96, vreg);
133 ra_class_add_reg(reg32low, i);
138 ra_class_add_reg(reg64low, i);
143 ra_class_add_reg(reg96, i);
156 ra_class_add_reg(low, i);
160 ra_class_add_reg(high, i);
177 ra_class_add_reg(c1, i);
181 ra_class_add_reg(c
[all...]
H A Dregister_allocate.h69 void ra_class_add_reg(struct ra_class *c, unsigned int reg);
H A Dregister_allocate.c268 ra_class_add_reg(struct ra_class *class, unsigned int r) function in typeref:typename:void
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/vc4/
H A Dvc4_register_allocate.c135 ra_class_add_reg(vc4->regs, vc4->reg_class_r0_r3, i);
136 ra_class_add_reg(vc4->regs, vc4->reg_class_a_or_b_or_acc[0], i);
137 ra_class_add_reg(vc4->regs, vc4->reg_class_a_or_b_or_acc[1], i);
144 ra_class_add_reg(vc4->regs, vc4->reg_class_r4_or_a[i],
146 ra_class_add_reg(vc4->regs, vc4->reg_class_any[i],
158 ra_class_add_reg(vc4->regs, vc4->reg_class_any[0], i);
159 ra_class_add_reg(vc4->regs, vc4->reg_class_a_or_b[0], i);
160 ra_class_add_reg(vc4->regs, vc4->reg_class_a_or_b_or_acc[0], i);
163 ra_class_add_reg(vc4->regs, vc4->reg_class_any[1], i);
164 ra_class_add_reg(vc
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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/vc4/
H A Dvc4_register_allocate.c135 ra_class_add_reg(vc4->reg_class_r0_r3, i);
136 ra_class_add_reg(vc4->reg_class_a_or_b_or_acc[0], i);
137 ra_class_add_reg(vc4->reg_class_a_or_b_or_acc[1], i);
144 ra_class_add_reg(vc4->reg_class_r4_or_a[i], ACC_INDEX + 4);
145 ra_class_add_reg(vc4->reg_class_any[i], ACC_INDEX + 4);
156 ra_class_add_reg(vc4->reg_class_any[0], i);
157 ra_class_add_reg(vc4->reg_class_a_or_b[0], i);
158 ra_class_add_reg(vc4->reg_class_a_or_b_or_acc[0], i);
161 ra_class_add_reg(vc4->reg_class_any[1], i);
162 ra_class_add_reg(vc
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/xsrc/external/mit/MesaLib.old/dist/src/util/
H A Dregister_allocate.h59 void ra_class_add_reg(struct ra_regs *regs, unsigned int c, unsigned int reg);
H A Dregister_allocate.c321 ra_class_add_reg(struct ra_regs *regs, unsigned int c, unsigned int r) function in typeref:typename:void
/xsrc/external/mit/MesaLib/dist/src/broadcom/compiler/
H A Dvir_register_allocate.c514 ra_class_add_reg(compiler->reg_class_phys_or_acc[threads], i);
515 ra_class_add_reg(compiler->reg_class_phys[threads], i);
516 ra_class_add_reg(compiler->reg_class_any[threads], i);
520 ra_class_add_reg(compiler->reg_class_phys_or_acc[threads], i);
521 ra_class_add_reg(compiler->reg_class_any[threads], i);
526 ra_class_add_reg(compiler->reg_class_r5[threads],
528 ra_class_add_reg(compiler->reg_class_any[threads],
/xsrc/external/mit/MesaLib.old/dist/src/broadcom/compiler/
H A Dvir_register_allocate.c375 ra_class_add_reg(compiler->regs,
377 ra_class_add_reg(compiler->regs,
379 ra_class_add_reg(compiler->regs,
384 ra_class_add_reg(compiler->regs,
386 ra_class_add_reg(compiler->regs,
392 ra_class_add_reg(compiler->regs,
395 ra_class_add_reg(compiler->regs,
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/etnaviv/
H A Detnaviv_compiler_nir_ra.c98 ra_class_add_reg(classes[reg_get_class(r)], r);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/lima/ir/pp/
H A Dregalloc.c65 ra_class_add_reg(classes[i], j + swiz);
74 ra_class_add_reg(classes[i], j);
/xsrc/external/mit/MesaLib.old/dist/src/freedreno/ir3/
H A Dir3_ra.c228 ra_class_add_reg(set->regs, set->classes[i], reg);
250 ra_class_add_reg(set->regs, set->half_classes[i], reg);
272 ra_class_add_reg(set->regs, set->high_classes[i], reg);
/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dbrw_fs_reg_allocate.cpp213 ra_class_add_reg(regs, classes[i], reg);
227 ra_class_add_reg(regs, classes[i], reg);
257 ra_class_add_reg(regs, aligned_pairs_class, pairs_base_reg + i);
H A Dbrw_vec4_reg_allocate.cpp134 ra_class_add_reg(compiler->vec4_reg_set.regs, compiler->vec4_reg_set.classes[i], reg);
/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_fs_reg_allocate.cpp145 ra_class_add_reg(classes[i], reg);
148 ra_class_add_reg(classes[i], reg);
161 ra_class_add_reg(aligned_bary_class, i);
H A Dbrw_vec4_reg_allocate.cpp124 ra_class_add_reg(compiler->vec4_reg_set.classes[i], j);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r300/compiler/
H A Dradeon_pair_regalloc.c709 ra_class_add_reg(s->regs,
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/lima/ir/pp/
H A Dregalloc.c130 ra_class_add_reg(ret, i, reg_index++);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r300/compiler/
H A Dradeon_pair_regalloc.c709 ra_class_add_reg(s->classes[class->ID], reg_id);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/panfrost/midgard/
H A Dmidgard_compile.c2193 ra_class_add_reg(regs, primary_class, i);
2196 ra_class_add_reg(regs, varying_class, REGISTER_VARYING_BASE);
2197 ra_class_add_reg(regs, varying_class, REGISTER_VARYING_BASE + 1);

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