Searched refs:restore (Results 1 - 25 of 236) sorted by relevance

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/xsrc/external/mit/xf86-video-siliconmotion/dist/src/
H A Dsmilynx_hw.c145 * This function performs the inverse of the restore function: It saves all the
320 * This function is used to restore a video mode. It writes out all of the
325 SMILynx_WriteMode(ScrnInfoPtr pScrn, vgaRegPtr vgaSavePtr, SMIRegPtr restore) argument
338 VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x17, restore->SR17);
339 VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x18, restore->SR18);
341 VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x20, restore->SR20);
342 VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x21, restore->SR21);
343 VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x22, restore->SR22);
344 VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x23, restore->SR23);
345 VGAOUT8_INDEX(pSmi, VGA_SEQ_INDEX, VGA_SEQ_DATA, 0x24, restore
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H A Dsmi_501.c140 /* Also save accel state to properly restore kernel framebuffer */
366 SMI501_WriteMode(ScrnInfoPtr pScrn, MSOCRegPtr restore) argument
370 SMI501_WriteMode_common(pScrn, restore);
371 SMI501_WriteMode_lcd(pScrn, restore);
372 SMI501_WriteMode_crt(pScrn, restore);
374 SMI501_WriteMode_alpha(pScrn, restore);
378 WRITE_SCR(pSmi, ACCEL_SRC, restore->accel_src);
379 WRITE_SCR(pSmi, ACCEL_DST, restore->accel_dst);
380 WRITE_SCR(pSmi, ACCEL_DIM, restore->accel_dim);
381 WRITE_SCR(pSmi, ACCEL_CTL, restore
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/xsrc/external/mit/xf86-video-ati/dist/src/
H A Dradeon_tv.c351 RADEONRestoreTVTimingTables(ScrnInfoPtr pScrn, RADEONSavePtr restore) argument
360 OUTREG(RADEON_TV_UV_ADR, restore->tv_uv_adr);
361 hTable = RADEONGetHTimingTablesAddr(restore->tv_uv_adr);
362 vTable = RADEONGetVTimingTablesAddr(restore->tv_uv_adr);
365 tmp = ((uint32_t)restore->h_code_timing[ i ] << 14) | ((uint32_t)restore->h_code_timing[ i + 1 ]);
367 if (restore->h_code_timing[ i ] == 0 || restore->h_code_timing[ i + 1 ] == 0)
372 tmp = ((uint32_t)restore->v_code_timing[ i + 1 ] << 14) | ((uint32_t)restore
381 RADEONRestoreTVPLLRegisters(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
404 RADEONRestoreTVHVRegisters(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
430 RADEONRestoreTVRestarts(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
442 RADEONRestoreTVOutputStd(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
461 RADEONRestoreTVRegisters(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
1056 RADEONSavePtr restore = info->ModeReg; local in function:RADEONUpdateHVPosition
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H A Dlegacy_crtc.c62 RADEONSavePtr restore)
71 OUTREG(RADEON_OVR_CLR, restore->ovr_clr);
72 OUTREG(RADEON_OVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right);
73 OUTREG(RADEON_OVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom);
74 OUTREG(RADEON_OV0_SCALE_CNTL, restore->ov0_scale_cntl);
75 OUTREG(RADEON_SUBPIC_CNTL, restore->subpic_cntl);
76 OUTREG(RADEON_VIPH_CONTROL, restore->viph_control);
77 OUTREG(RADEON_I2C_CNTL_1, restore->i2c_cntl_1);
78 OUTREG(RADEON_GEN_INT_CNTL, restore->gen_int_cntl);
79 OUTREG(RADEON_CAP0_TRIG_CNTL, restore
61 RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
108 RADEONRestoreCrtcBase(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
121 RADEONRestoreCrtc2Base(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
135 RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
179 RADEONRestoreCrtc2Registers(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
299 RADEONRestorePLLRegisters(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
424 RADEONRestorePLL2Registers(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
1362 radeon_update_tv_routing(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
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H A Dradeon_driver.c323 * two channels with the two channels configured differently), restore
2317 * is enabled. Clear and restore FP2_ON around int10 to avoid this.
3756 /* restore the memory map here otherwise we may get a hang when
3790 * our local image to make sure we restore them properly on mode
3938 RADEONSavePtr restore)
3955 (unsigned)restore->mc_fb_location, (unsigned int)mc_fb_loc);
3958 (unsigned)restore->mc_agp_location);
3961 if (mc_fb_loc != restore->mc_fb_location ||
3962 mc_agp_loc != restore->mc_agp_location) {
4023 restore
3937 RADEONRestoreMemMapRegisters(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
4285 RADEONRestoreSurfaces(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
4498 RADEONRestorePalette(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
4872 dce4_restore(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
5268 avivo_restore(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
5663 avivo_restore_vga_regs(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
5674 dce4_restore_vga_regs(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
5691 RADEONRestoreBIOSRegisters(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
5829 RADEONSavePtr restore = info->SavedReg; local in function:RADEONRestore
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H A Dlegacy_output.c247 RADEONSavePtr restore)
253 OUTREGP(RADEON_GPIOPAD_A, restore->gpiopad_a, ~1);
256 restore->dac_cntl,
260 OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl);
264 OUTREG (RADEON_TV_DAC_CNTL, restore->tv_dac_cntl);
266 OUTREG(RADEON_DISP_OUTPUT_CNTL, restore->disp_output_cntl);
270 OUTREG(RADEON_DISP_TV_OUT_CNTL, restore->disp_tv_out_cntl);
272 OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug);
275 OUTREG(RADEON_DAC_MACRO_CNTL, restore->dac_macro_cntl);
279 OUTREG(RADEON_FP2_GEN_CNTL, restore
246 RADEONRestoreDACRegisters(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
285 RADEONRestoreFPRegisters(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
313 RADEONRestoreFP2Registers(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
327 RADEONRestoreRMXRegisters(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
345 RADEONRestoreLVDSRegisters(ScrnInfoPtr pScrn,RADEONSavePtr restore) argument
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/xsrc/external/mit/xterm/dist/vttests/
H A Dtab0.sh79 restore() { function
118 restore
H A Ddynamic2.sh108 eval restore=\$original"$N"
109 $CMD $OPT "$restore" >/dev/tty
/xsrc/external/mit/xf86-video-s3/dist/src/
H A Ds3_Trio64DAC.c112 S3RegPtr restore = &pS3->SavedRegs; local in function:S3Trio64DAC_Restore
115 outb(0x3c2, restore->dacregs[0]);
120 outb(0x3c5, restore->dacregs[2]);
122 outb(0x3c5, restore->dacregs[3]);
124 outb(0x3c5, restore->dacregs[4]);
126 outb(0x3c5, restore->dacregs[5]);
129 outb(0x3c5, restore->dacregs[8]);
131 outb(0x3c5, restore->dacregs[9]);
133 outb(0x3c5, restore->dacregs[10]);
135 outb(0x3c5, restore
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H A Ds3_Ti.c267 S3RegPtr restore = &pS3->SavedRegs; local in function:S3TiDAC_Restore
270 restore->dacregs[TIDAC_true_color_ctrl]);
272 restore->dacregs[TIDAC_multiplex_ctrl]);
274 restore->dacregs[TIDAC_clock_select]);
276 restore->dacregs[TIDAC_output_clock_select]);
278 restore->dacregs[TIDAC_general_ctrl]);
280 restore->dacregs[TIDAC_auxiliary_ctrl]);
283 restore->dacregs[TIDAC_general_io_data]);
286 restore->dacregs[TIDAC_pll_addr]);
288 restore
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H A Ds3_GENDAC.c117 for(i = 0; i < 2 * 3; i++) /* restore first two LUT entries */
338 S3RegPtr restore = &pS3->SavedRegs; local in function:S3GENDAC_Restore
345 outb(0x3c6, restore->dacregs[0]); /* Enhanced command register */
347 outb(0x3c9, restore->dacregs[3]); /* f2 PLL M divider */
348 outb(0x3c9, restore->dacregs[4]); /* f2 PLL N1/N2 divider */
350 outb(0x3c9, restore->dacregs[5]); /* PLL control */
351 outb(0x3c8, restore->dacregs[2]); /* PLL write index */
352 outb(0x3c7, restore->dacregs[1]); /* PLL read index */
/xsrc/external/mit/xf86-video-r128/dist/src/
H A Dr128_crtc.c253 void R128RestoreCrtcRegisters(ScrnInfoPtr pScrn, R128SavePtr restore) argument
258 OUTREG(R128_CRTC_GEN_CNTL, restore->crtc_gen_cntl);
260 OUTREGP(R128_CRTC_EXT_CNTL, restore->crtc_ext_cntl,
263 OUTREG(R128_CRTC_H_TOTAL_DISP, restore->crtc_h_total_disp);
264 OUTREG(R128_CRTC_H_SYNC_STRT_WID, restore->crtc_h_sync_strt_wid);
265 OUTREG(R128_CRTC_V_TOTAL_DISP, restore->crtc_v_total_disp);
266 OUTREG(R128_CRTC_V_SYNC_STRT_WID, restore->crtc_v_sync_strt_wid);
267 OUTREG(R128_CRTC_OFFSET, restore->crtc_offset);
268 OUTREG(R128_CRTC_OFFSET_CNTL, restore->crtc_offset_cntl);
269 OUTREG(R128_CRTC_PITCH, restore
273 R128RestoreCrtc2Registers(ScrnInfoPtr pScrn,R128SavePtr restore) argument
493 R128RestorePLLRegisters(ScrnInfoPtr pScrn,R128SavePtr restore) argument
568 R128RestorePLL2Registers(ScrnInfoPtr pScrn,R128SavePtr restore) argument
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H A Dr128_driver.c2234 void R128RestoreCommonRegisters(ScrnInfoPtr pScrn, R128SavePtr restore) argument
2239 OUTREG(R128_FP_GEN_CNTL, restore->fp_gen_cntl | R128_FP_BLANK_DIS);
2241 OUTREG(R128_OVR_CLR, restore->ovr_clr);
2242 OUTREG(R128_OVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right);
2243 OUTREG(R128_OVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom);
2244 OUTREG(R128_OV0_SCALE_CNTL, restore->ov0_scale_cntl);
2245 OUTREG(R128_MPP_TB_CONFIG, restore->mpp_tb_config );
2246 OUTREG(R128_MPP_GP_CONFIG, restore->mpp_gp_config );
2247 OUTREG(R128_SUBPIC_CNTL, restore->subpic_cntl);
2248 OUTREG(R128_VIPH_CONTROL, restore
2258 R128RestoreRMXRegisters(ScrnInfoPtr pScrn,R128SavePtr restore) argument
2272 R128RestoreFPRegisters(ScrnInfoPtr pScrn,R128SavePtr restore) argument
2284 R128RestoreLVDSRegisters(ScrnInfoPtr pScrn,R128SavePtr restore) argument
2313 R128RestoreDDARegisters(ScrnInfoPtr pScrn,R128SavePtr restore) argument
2323 R128RestoreDDA2Registers(ScrnInfoPtr pScrn,R128SavePtr restore) argument
2562 R128SavePtr restore = &info->SavedReg; local in function:R128Restore
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H A Dr128.h540 extern void R128RestoreCommonRegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
541 extern void R128RestoreDACRegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
542 extern void R128RestoreRMXRegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
543 extern void R128RestoreFPRegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
544 extern void R128RestoreLVDSRegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
545 extern void R128RestoreCrtcRegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
546 extern void R128RestorePLLRegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
547 extern void R128RestoreDDARegisters(ScrnInfoPtr pScrn, R128SavePtr restore);
548 extern void R128RestoreCrtc2Registers(ScrnInfoPtr pScrn, R128SavePtr restore);
549 extern void R128RestorePLL2Registers(ScrnInfoPtr pScrn, R128SavePtr restore);
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/xsrc/external/mit/xf86-video-mga/dist/src/
H A Dmga_vga.c20 MGAG200SERestoreFonts(ScrnInfoPtr scrninfp, vgaRegPtr restore) argument
112 /* restore the registers that were changed */
246 MGAG200SERestoreMode(ScrnInfoPtr scrninfp, vgaRegPtr restore) argument
253 if (restore->MiscOutReg & 0x01)
258 hwp->writeMiscOut(hwp, restore->MiscOutReg);
261 for (i = 1; i < restore->numSequencer; i++)
265 hwp->writeSeq(hwp, i, restore->Sequencer[i]);
278 hwp->writeCrtc(hwp, 17, restore->CRTC[17] & ~0x80);
280 for (i = 0; i < restore->numCRTC; i++)
281 hwp->writeCrtc(hwp, i, restore
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/xsrc/external/mit/xf86-video-intel-old/dist/src/
H A Di2c_vid.h58 void (*restore)(I2CDevPtr d); member in struct:_I830I2CVidOutputRec
/xsrc/external/mit/xf86-video-neomagic/dist/src/
H A Dneo_driver.c133 NeoRegPtr restore);
2173 * routines will restore the proper values on server exit.
2176 neoProgramShadowRegs(ScrnInfoPtr pScrn, vgaRegPtr VgaReg, NeoRegPtr restore) argument
2204 if (restore->PanelDispCntlReg2 & 0x84) {
2225 if (restore->PanelDispCntlReg2 & 0x84) {
2419 neoRestore(ScrnInfoPtr pScrn, vgaRegPtr VgaReg, NeoRegPtr restore, argument
2433 neoProgramShadowRegs(pScrn, VgaReg, restore);
2437 VGAwGR(0x0A,restore->GeneralLockReg);
2451 temp |= (restore->ExtColorModeSelect & ~0xF0);
2462 temp |= (restore
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/xsrc/external/mit/xorg-server.old/dist/hw/xfree86/vgahw/
H A DvgaHW.h202 extern _X_EXPORT void vgaHWRestoreFonts(ScrnInfoPtr scrninfp, vgaRegPtr restore);
203 extern _X_EXPORT void vgaHWRestoreMode(ScrnInfoPtr scrninfp, vgaRegPtr restore);
204 extern _X_EXPORT void vgaHWRestoreColormap(ScrnInfoPtr scrninfp, vgaRegPtr restore);
205 extern _X_EXPORT void vgaHWRestore(ScrnInfoPtr scrninfp, vgaRegPtr restore, int flags);
H A DvgaHW.c729 vgaHWRestoreFonts(ScrnInfoPtr scrninfp, vgaRegPtr restore) argument
822 /* restore the registers that were changed */
843 vgaHWRestoreMode(ScrnInfoPtr scrninfp, vgaRegPtr restore) argument
848 if (restore->MiscOutReg & 0x01)
853 hwp->writeMiscOut(hwp, restore->MiscOutReg);
855 for (i = 1; i < restore->numSequencer; i++)
856 hwp->writeSeq(hwp, i, restore->Sequencer[i]);
859 hwp->writeCrtc(hwp, 17, restore->CRTC[17] & ~0x80);
861 for (i = 0; i < restore->numCRTC; i++)
862 hwp->writeCrtc(hwp, i, restore
875 vgaHWRestoreColormap(ScrnInfoPtr scrninfp,vgaRegPtr restore) argument
901 vgaHWRestore(ScrnInfoPtr scrninfp,vgaRegPtr restore,int flags) argument
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/xsrc/external/mit/xorg-server/dist/hw/xfree86/vgahw/
H A DvgaHW.h197 vgaRegPtr restore);
198 extern _X_EXPORT void vgaHWRestoreMode(ScrnInfoPtr scrninfp, vgaRegPtr restore);
200 vgaRegPtr restore);
201 extern _X_EXPORT void vgaHWRestore(ScrnInfoPtr scrninfp, vgaRegPtr restore,
/xsrc/external/mit/ctwm/dist/
H A Dwin_utils.h17 int restore_mask(Window w, long restore);
/xsrc/external/mit/xf86-video-s3virge/dist/src/
H A Ds3v_driver.c1395 * to restore the previous (text) mode.
1427 * This function performs the inverse of the restore function: It saves all
1740 * This function is used to restore a video mode. It writes out all
1751 S3VWriteMode (ScrnInfoPtr pScrn, vgaRegPtr vgaSavePtr, S3VRegPtr restore) argument
1767 ps3v->STREAMSRunning = restore->CR67 & 0x0c;
1788 VGAOUT8(vgaCRReg, restore->CR63);
1790 VGAOUT8(vgaCRReg, restore->CR66);
1792 VGAOUT8(vgaCRReg, restore->CR3A);
1794 VGAOUT8(vgaCRReg, restore->CR31);
1796 VGAOUT8(vgaCRReg, restore
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/xsrc/external/mit/xf86-video-savage/dist/src/
H A Dsavage_driver.c2465 SavageRegPtr restore, Bool Entering)
2477 TRACE(("SavageWriteMode(%x)\n", restore->mode));
2488 SavageSetVESAMode( psav, restore->mode | 0x8000, restore->refresh );
2503 if( psav->UseBIOS && restore->mode > 0x13 )
2510 SavageSetVESAMode( psav, restore->mode | 0x8000, restore->refresh );
2544 VGAOUT8(vgaCRReg, restore->CR67);
2574 if( restore->refresh >= 130 )
2580 (restore
2464 SavageWriteMode(ScrnInfoPtr pScrn,vgaRegPtr vgaSavePtr,SavageRegPtr restore,Bool Entering) argument
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/xsrc/external/mit/xterm/dist/
H A Dresize.c153 static const char *const restore[EMULATIONS] = variable in typeref:typename:const char * const[]
541 if (restore[emu])
542 IGNORE_RC(write(tty, restore[emu], strlen(restore[emu])));
/xsrc/external/mit/xf86-video-nv/dist/src/
H A Driva_dac.c165 int restore = VGA_SR_MODE; local in function:RivaDACRestore
167 restore |= primary ? (VGA_SR_CMAP | VGA_SR_FONTS) : VGA_SR_CMAP;
169 vgaHWRestore(pScrn, vgaReg, restore);

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