| /src/sys/arch/hpcsh/hpcsh/ |
| debug.c | 46 int phase; member in struct:intr_state_rgb16
73 intr_state_rgb16->cnt = 0, intr_state_rgb16->phase ^= 1;
78 intr_state_rgb16->phase ? ~color : color;
|
| /src/sys/arch/arm/sunxi/ |
| sunxi_ccu_phase.c | 61 struct sunxi_ccu_phase *phase = &clk->u.phase; local in function:sunxi_ccu_phase_get_rate
77 val = CCU_READ(sc, phase->reg);
78 delay = __SHIFTOUT(val, phase->mask);
87 struct sunxi_ccu_phase *phase = &clk->u.phase; local in function:sunxi_ccu_phase_set_rate
109 val = CCU_READ(sc, phase->reg);
110 val &= ~phase->mask;
111 val |= __SHIFTIN(delay, phase->mask);
112 CCU_WRITE(sc, phase->reg, val)
121 struct sunxi_ccu_phase *phase = &clk->u.phase; local in function:sunxi_ccu_phase_get_parent
[all...] |
| /src/sys/dev/rcons/ |
| raster_text.c | 93 int phase; local in function:raster_textn
143 phase = 0;
209 rop, charrast, phase, 0 ) < 0 )
216 rop, charrast, phase, 0 ) < 0 )
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_dccg.c | 58 int modulo, phase; local in function:dccg2_update_dpp_dto
60 // phase / modulo = dpp pipe clk / dpp global clk
62 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk;
64 if (phase > 0xff) {
66 phase = 0xff;
70 DPPCLK0_DTO_PHASE, phase,
|
| amdgpu_dcn20_dwb_scl.c | 694 int phase; local in function:wbscl_set_scaler_filter
698 for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) {
700 even_coef = filter[phase * taps + 2 * pair];
702 odd_coef = filter[phase * taps + 2 * pair + 1];
708 WBSCL_COEF_RAM_PHASE, phase,
762 /* Calculate phase*/
781 /* Program phase*/
840 /* Calculate phase*/
[all...] |
| /src/sbin/ifconfig/ |
| af_atalk.c | 74 struct pinteger phase = PINTEGER_INITIALIZER1(&phase, "phase", variable in typeref:struct:pinteger
75 1, 2, 10, NULL, "phase", &command_root.pb_parser);
81 {.k_word = "phase", .k_nextparser = &phase.pi_parser}
151 (void)prop_dictionary_get_uint8(env, "phase", &nr.nr_phase);
|
| /src/tests/dev/audio/ |
| h_pad.c | 112 } phase; local in function:main
170 phase = PRE;
190 if (phase == PRE) {
197 phase = BODY;
199 } else if (phase == BODY) {
212 phase = POST;
215 } else if (phase == POST) {
|
| /src/sys/external/bsd/drm2/dist/drm/i915/selftests/ |
| i915_syncmap.c | 552 unsigned long count, phase, i; local in function:igt_syncmap_random
565 phase = jiffies + HZ/100 + 1;
574 } while (!time_after(jiffies, phase));
577 phase = 0;
601 phase++;
603 pr_debug("Completed %lu passes, each of %lu contexts\n", phase, count);
|
| i915_vma.c | 709 const struct phase { struct in function:igt_vma_partial
|
| /src/sys/arch/hp300/stand/common/ |
| scsi.c | 210 ixfer_start(volatile struct scsidevice *hd, int len, uint8_t phase, int wait)
216 hd->scsi_pctl = phase;
271 uint8_t phase, ints; local in function:scsiicmd
280 * Wait for a phase change (or error) then let the device
284 phase = CMD_PHASE;
287 switch (phase) {
290 if (ixfer_start(hd, clen, phase, wait))
293 phase = xferphase;
300 if (ixfer_start(hd, len, phase, wait) ||
303 phase = STATUS_PHASE
[all...] |
| /src/sys/arch/acorn32/podulebus/ |
| esc.c | 574 int len, mode, phase;
581 * Decode the scsi phase to determine whether we are reading or writing.
584 phase = dev->sc_status & ESC_STAT_PHASE_MASK;
585 mode = (phase == ESC_PHASE_DATA_IN);
587 while(len && ((dev->sc_status & ESC_STAT_PHASE_MASK) == phase))
608 * Since the last esciwait will be a phase-change, we can't wait for it
628 int len, mode, phase; local in function:esc_ixfer
642 * Decode the scsi phase to determine whether we are reading or writing.
645 phase = dev->sc_status & ESC_STAT_PHASE_MASK;
646 mode = (phase == ESC_PHASE_DATA_IN)
[all...] |
| sfas.c | 574 int len, mode, phase; local in function:sfas_ixfer
581 * Decode the scsi phase to determine whether we are reading or writing.
584 phase = dev->sc_status & SFAS_STAT_PHASE_MASK;
585 mode = (phase == SFAS_PHASE_DATA_IN);
587 while(len && ((dev->sc_status & SFAS_STAT_PHASE_MASK) == phase))
608 * Since the last sfasiwait will be a phase-change, we can't wait for it
1194 * Part three of the interrupt machine. Handle phase changes (and repeated
1195 * phase passes). We know that we have an active nexus here.
1287 * We've got status phase. Request status and command
1502 printf("SFASINTR: UNKNOWN PHASE! phase: %d\n"
[all...] |
| /src/sys/dev/usb/ |
| motgvar.h | 60 usb_phase_t phase; /* current phase of the transfer, if any */ member in struct:motg_hw_ep
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/ |
| amdgpu_dce110_transform_v.c | 297 int i, phase, pair; local in function:program_multi_taps_filter
327 for (phase = 0; phase < phases_to_program; phase++) {
329 phase 0 is unique and phase N/2 is unique if N is even*/
330 set_reg_field_value(select, phase, SCLV_COEF_RAM_SELECT, SCL_C_RAM_PHASE);
|
| /src/sys/external/bsd/drm2/dist/drm/i915/gvt/ |
| edid.h | 114 enum gvt_gmbus_phase phase; member in struct:intel_vgpu_i2c_gmbus
|
| /src/sys/arch/sgimips/stand/common/ |
| iris_scsi.c | 181 /* Handle the new phase */
216 * Returns the current CSR following selection and optionally MSG out phase.
217 * i.e. the returned CSR *should* indicate CMD phase...
437 * Message out phase. ATN signal has been asserted
478 * CMD phase until the disk has spun up. Only then will the target change
479 * to STATUS phase. This is really only a problem for immediate commands
614 uint8_t phase, csr; local in function:wd33c93_xferdone
633 GET_SBIC_cmd_phase(sc, phase);
635 if (phase == 0x60)
763 * Handle message_in phase
[all...] |
| /src/sys/arch/amiga/dev/ |
| sci.c | 205 int flags, phase, stat; local in function:sci_donextcmd
212 phase = DATA_IN_PHASE;
214 phase = DATA_OUT_PHASE;
216 phase = STATUS_PHASE;
223 if (phase == STATUS_PHASE || flags & XS_CTL_POLL)
225 xs->data, xs->datalen, phase);
406 int phase)
415 *dev->sci_tcmd = phase;
446 sci_ixfer_in(struct sci_softc *dev, int len, register u_char *buf, int phase)
461 *dev->sci_tcmd = phase;
508 u_char phase; local in function:sciicmd
600 u_char phase, *addr; local in function:scigo
[all...] |
| /src/sys/ufs/lfs/ |
| lfs_rfw.c | 556 kauth_cred_t cred, int phase, int *pseg_flags, struct lwp *l)
598 * Phase I: Check summary checksum.
600 if (phase == CHECK_CKSUM) {
656 if (phase == CHECK_CKSUM) {
668 if (phase == CHECK_GEN) {
675 if (phase == CHECK_INODES) {
694 if (phase == CHECK_CKSUM) {
706 if (phase == CHECK_DATA &&
722 if (phase == CHECK_CKSUM) {
734 if (phase == CHECK_CKSUM
782 int flags, dirty, phase; local in function:lfs_roll_forward
[all...] |
| /src/sys/arch/newsmips/apbus/ |
| spifi.c | 519 * XXX dataout phase.
543 int phase; local in function:spifi_pmatch
545 phase = (reg->prstat & PRS_PHASE);
548 printf("%s (%s)\n", __func__, scsi_phase_name[phase >> 3]);
551 switch (phase) {
567 printf("spifi: unknown phase %d\n", phase);
670 int phase; local in function:spifi_data_io
674 phase = reg->prstat & PRS_PHASE;
682 if (phase == SPIFI_DATAIN)
[all...] |
| /src/sys/dev/scsipi/ |
| atapi_wdc.c | 739 int len, phase, i, retries=0; local in function:wdc_atapi_intr
845 phase = (ire & (WDCI_CMD | WDCI_IN)) | (ATACH_ST(tfd) & WDCS_DRQ);
850 switch (phase) {
903 printf("wdc_atapi_intr: bad data phase DATAOUT\n");
957 printf("wdc_atapi_intr: bad data phase DATAIN\n");
1028 printf("wdc_atapi_intr: unknown phase 0x%x\n", phase);
|
| /src/sys/arch/dreamcast/dev/maple/ |
| mlcd.c | 64 uint8_t phase; /* 0, 1, 2, 3: for each 128 byte */ member in struct:mlcd_request_write_data
384 sc->sc_reqw.phase = 0;
414 if (++sc->sc_reqw.phase == sc->sc_wacc) {
415 /* all phase done */
418 /* go next phase */
421 sc->sc_waccsz * sc->sc_reqw.phase,
457 printf(" Phase error");
559 * Start the first phase (phase# = 0).
566 sc->sc_reqw.phase = 0; /* first phase *
[all...] |
| /src/sys/arch/mac68k/dev/ |
| ncr5380reg.h | 99 #define SC_PHS_MTCH 0x08 /* R - Phase Match */
125 #define PH_OUT(phase) (!(phase & 1)) /* TRUE if output phase */
126 #define PH_IN(phase) (phase & 1) /* TRUE if input phase */
162 * command phase (ignoring ATN), then we flag it in the
194 u_char phase; /* current SCSI phase */ member in struct:req_q
[all...] |
| /src/sys/dev/ic/ |
| sunscpal.c | 56 * Gordon Ross integrated the message phase code, added lots of
125 #define ACT_CONTINUE 0x00 /* No flags: expect another phase */
195 /* This one is used when waiting for a phase change. (X100uS.) */
416 /* Ask the target for a MSG_OUT phase. */
431 sunscpal_pio_out(struct sunscpal_softc *sc, int phase, int count, uint8_t *data)
446 phase)
451 SUNSCPAL_BYTE_WRITE(sc, phase, *data++);
453 SUNSCPAL_BYTE_WRITE(sc, phase, 0);
464 sunscpal_pio_in(struct sunscpal_softc *sc, int phase, int count, uint8_t *data)
478 /* A phase change is not valid until AFTER REQ rises! *
1296 int n, phase; local in function:sunscpal_msg_in
1670 int act_flags, phase, timo; local in function:sunscpal_machine
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_dpp_dscl.c | 69 /* Autocal calculate the scaling ratio and initial phase and the
270 int phase; local in function:dpp1_dscl_set_scaler_filter
279 for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) {
281 even_coef = filter[phase * taps + 2 * pair];
283 odd_coef = filter[phase * taps + 2 * pair + 1];
|
| /src/sys/arch/atari/dev/ |
| ncr5380reg.h | 99 #define SC_PHS_MTCH 0x08 /* R - Phase Match */
125 #define PH_OUT(phase) (!(phase & 1)) /* TRUE if output phase */
126 #define PH_IN(phase) (phase & 1) /* TRUE if input phase */
162 * command phase (ignoring ATN), then we flag it in the
194 uint8_t phase; /* current SCSI phase */ member in struct:req_q
[all...] |
