HomeSort by: relevance | last modified time | path
    Searched refs:RREG32 (Results 1 - 25 of 144) sorted by relevancy

1 2 3 4 5 6

  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_vce_v2_0.c 48 tmp = RREG32(VCE_CLOCK_GATING_B);
52 tmp = RREG32(VCE_UENC_CLOCK_GATING);
56 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
62 tmp = RREG32(VCE_CLOCK_GATING_B);
67 tmp = RREG32(VCE_UENC_CLOCK_GATING);
72 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
82 tmp = RREG32(VCE_CLOCK_GATING_B);
92 orig = tmp = RREG32(VCE_UENC_CLOCK_GATING);
98 orig = tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
139 tmp = RREG32(VCE_CLOCK_GATING_A)
    [all...]
radeon_bios.c 330 bus_cntl = RREG32(R600_BUS_CNTL);
331 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
332 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
333 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
334 rom_cntl = RREG32(R600_ROM_CNTL);
376 viph_control = RREG32(RADEON_VIPH_CONTROL);
377 bus_cntl = RREG32(R600_BUS_CNTL);
378 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
379 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
380 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL)
    [all...]
radeon_vce_v1_0.c 68 return RREG32(VCE_RB_RPTR);
70 return RREG32(VCE_RB_RPTR2);
85 return RREG32(VCE_RB_WPTR);
87 return RREG32(VCE_RB_WPTR2);
112 tmp = RREG32(VCE_CLOCK_GATING_A);
116 tmp = RREG32(VCE_UENC_CLOCK_GATING);
121 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
125 tmp = RREG32(VCE_CLOCK_GATING_A);
129 tmp = RREG32(VCE_UENC_CLOCK_GATING);
134 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING)
    [all...]
radeon_i2c.c 139 temp = RREG32(rec->mask_clk_reg);
145 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
148 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
152 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
155 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
159 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
161 temp = RREG32(rec->mask_clk_reg);
163 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
165 temp = RREG32(rec->mask_data_reg);
178 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask
    [all...]
radeon_legacy_encoders.c 69 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
97 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
100 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
105 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
200 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
203 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
210 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
221 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
291 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
365 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >
    [all...]
radeon_rs600.c 68 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
78 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
79 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
102 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
126 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
143 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
159 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
237 tmp = RREG32(voltage->gpio.reg);
246 tmp = RREG32(voltage->gpio.reg);
332 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset)
    [all...]
radeon_rv730_dpm.c 207 RREG32(CG_SPLL_FUNC_CNTL);
209 RREG32(CG_SPLL_FUNC_CNTL_2);
211 RREG32(CG_SPLL_FUNC_CNTL_3);
213 RREG32(CG_SPLL_SPREAD_SPECTRUM);
215 RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
218 RREG32(TCI_MCLK_PWRMGT_CNTL);
220 RREG32(TCI_DLL_CNTL);
222 RREG32(CG_MPLL_FUNC_CNTL);
224 RREG32(CG_MPLL_FUNC_CNTL_2);
226 RREG32(CG_MPLL_FUNC_CNTL_3)
    [all...]
radeon_rs400.c 163 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
167 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
254 tmp = RREG32(RADEON_MC_STATUS);
269 RREG32(RADEON_MC_STATUS));
283 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
297 r = RREG32(RS480_NB_MC_DATA);
322 tmp = RREG32(RADEON_HOST_PATH_CNTL);
324 tmp = RREG32(RADEON_BUS_CNTL);
337 tmp = RREG32(RS690_HDP_FB_LOCATION);
340 tmp = RREG32(RADEON_AGP_BASE)
    [all...]
radeon_trinity_smc.c 41 if (RREG32(SMC_RESP_0) != 0)
45 v = RREG32(SMC_RESP_0);
122 if ((RREG32(SMC_INT_REQ) & 0xffff) == 1)
radeon_si_smc.c 91 original_data = RREG32(SMC_IND_DATA_0);
131 RREG32(CB_CGTT_SCLK_CTRL);
132 RREG32(CB_CGTT_SCLK_CTRL);
133 RREG32(CB_CGTT_SCLK_CTRL);
134 RREG32(CB_CGTT_SCLK_CTRL);
188 tmp = RREG32(SMC_RESP_0);
193 tmp = RREG32(SMC_RESP_0);
296 *value = RREG32(SMC_IND_DATA_0);
radeon_dp_auxch.c 104 tmp = RREG32(chan->rec.mask_clk_reg);
109 tmp = RREG32(AUX_CONTROL + aux_offset[instance]);
158 tmp = RREG32(AUX_SW_STATUS + aux_offset[instance]);
187 tmp = RREG32(AUX_SW_DATA + aux_offset[instance]);
191 tmp = RREG32(AUX_SW_DATA + aux_offset[instance]);
radeon_kv_smc.c 42 if ((RREG32(SMC_RESP_0) & SMC_RESP_MASK) != 0)
46 tmp = RREG32(SMC_RESP_0) & SMC_RESP_MASK;
102 *value = RREG32(SMC_IND_DATA_0);
143 original_data = RREG32(SMC_IND_DATA_0);
197 original_data= RREG32(SMC_IND_DATA_0);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_cik_ih.c 67 u32 ih_cntl = RREG32(mmIH_CNTL);
68 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
86 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
87 u32 ih_cntl = RREG32(mmIH_CNTL);
122 interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
208 tmp = RREG32(mmIH_RB_CNTL);
360 u32 tmp = RREG32(mmSRBM_STATUS);
376 tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK;
389 u32 tmp = RREG32(mmSRBM_STATUS);
395 tmp = RREG32(mmSRBM_SOFT_RESET)
    [all...]
amdgpu_gmc_v8_0.c 189 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
207 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
333 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
356 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
362 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
402 data = RREG32(mmMC_SEQ_MISC0);
426 data = RREG32(mmMC_SEQ_MISC0);
441 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
476 tmp = RREG32(mmVGA_HDP_CONTROL);
481 tmp = RREG32(mmVGA_RENDER_CONTROL)
    [all...]
amdgpu_vce_v2_0.c 65 return RREG32(mmVCE_RB_RPTR);
67 return RREG32(mmVCE_RB_RPTR2);
82 return RREG32(mmVCE_RB_WPTR);
84 return RREG32(mmVCE_RB_WPTR2);
110 uint32_t status = RREG32(mmVCE_LMI_STATUS);
127 uint32_t status = RREG32(mmVCE_STATUS);
156 tmp = RREG32(mmVCE_CLOCK_GATING_A);
162 tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
167 tmp = RREG32(mmVCE_CLOCK_GATING_B);
213 return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK)
    [all...]
amdgpu_si_ih.c 40 u32 ih_cntl = RREG32(IH_CNTL);
41 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
52 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
53 u32 ih_cntl = RREG32(IH_CNTL);
74 interrupt_cntl = RREG32(INTERRUPT_CNTL);
122 tmp = RREG32(IH_RB_CNTL);
220 u32 tmp = RREG32(SRBM_STATUS);
246 u32 tmp = RREG32(SRBM_STATUS);
252 tmp = RREG32(SRBM_SOFT_RESET);
256 tmp = RREG32(SRBM_SOFT_RESET)
    [all...]
amdgpu_cz_ih.c 67 u32 ih_cntl = RREG32(mmIH_CNTL);
68 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
86 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
87 u32 ih_cntl = RREG32(mmIH_CNTL);
122 interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
153 ih_cntl = RREG32(mmIH_CNTL);
210 tmp = RREG32(mmIH_RB_CNTL);
339 u32 tmp = RREG32(mmSRBM_STATUS);
355 tmp = RREG32(mmSRBM_STATUS);
367 u32 tmp = RREG32(mmSRBM_STATUS)
    [all...]
amdgpu_iceland_ih.c 67 u32 ih_cntl = RREG32(mmIH_CNTL);
68 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
86 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
87 u32 ih_cntl = RREG32(mmIH_CNTL);
122 interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
153 ih_cntl = RREG32(mmIH_CNTL);
210 tmp = RREG32(mmIH_RB_CNTL);
339 u32 tmp = RREG32(mmSRBM_STATUS);
355 tmp = RREG32(mmSRBM_STATUS);
367 u32 tmp = RREG32(mmSRBM_STATUS)
    [all...]
amdgpu_i2c.c 58 temp = RREG32(rec->mask_clk_reg);
64 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
67 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
71 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
74 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
78 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
80 temp = RREG32(rec->mask_clk_reg);
82 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
84 temp = RREG32(rec->mask_data_reg);
97 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask
    [all...]
amdgpu_gmc_v7_0.c 101 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
119 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
208 running = REG_GET_FIELD(RREG32(mmMC_SEQ_SUP_CNTL), MC_SEQ_SUP_CNTL, RUN);
231 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
237 if (REG_GET_FIELD(RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL),
250 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
285 tmp = RREG32(mmVGA_HDP_CONTROL);
290 tmp = RREG32(mmVGA_RENDER_CONTROL);
310 tmp = RREG32(mmHDP_MISC_CNTL);
314 tmp = RREG32(mmHDP_HOST_PATH_CNTL)
    [all...]
amdgpu_tonga_ih.c 67 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
84 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
118 interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
150 ih_doorbell_rtpr = RREG32(mmIH_DOORBELL_RPTR);
212 tmp = RREG32(mmIH_RB_CNTL);
350 u32 tmp = RREG32(mmSRBM_STATUS);
366 tmp = RREG32(mmSRBM_STATUS);
378 u32 tmp = RREG32(mmSRBM_STATUS);
425 tmp = RREG32(mmSRBM_SOFT_RESET);
429 tmp = RREG32(mmSRBM_SOFT_RESET)
    [all...]
amdgpu_amdkfd_arcturus.c 62 (*dump)[i++][1] = RREG32(addr); \
151 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
244 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
265 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL);
270 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS);
282 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) |
285 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR);
287 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI);
amdgpu_si_smc.c 91 original_data = RREG32(SMC_IND_DATA_0);
129 RREG32(CB_CGTT_SCLK_CTRL);
130 RREG32(CB_CGTT_SCLK_CTRL);
131 RREG32(CB_CGTT_SCLK_CTRL);
132 RREG32(CB_CGTT_SCLK_CTRL);
181 tmp = RREG32(SMC_RESP_0);
187 return (PPSMC_Result)RREG32(SMC_RESP_0);
259 *value = RREG32(SMC_IND_DATA_0);
amdgpu_kv_smc.c 45 if ((RREG32(mmSMC_RESP_0) & SMC_RESP_0__SMC_RESP_MASK) != 0)
49 tmp = RREG32(mmSMC_RESP_0) & SMC_RESP_0__SMC_RESP_MASK;
106 *value = RREG32(mmSMC_IND_DATA_0);
147 original_data = RREG32(mmSMC_IND_DATA_0);
201 original_data = RREG32(mmSMC_IND_DATA_0);
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_smu7_baco.c 50 reg = RREG32(mmCC_BIF_BX_FUSESTRAP0);
63 reg = RREG32(mmBACO_CNTL);

Completed in 19 milliseconds

1 2 3 4 5 6