| /src/sys/arch/evbppc/wii/ |
| pic_pi.c | 54 #define RD4(reg) in32(reg)
76 raw = RD4(PI_INTSR);
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| /src/sys/arch/arm/ti/ |
| ti_rng.c | 64 #define RD4(sc, reg) \
103 if ((RD4(sc, TRNG_CONTROL_REG) & TRNG_CONTROL_ENABLE) == 0) {
129 if (RD4(sc, TRNG_STATUS_REG) & TRNG_STATUS_READY)
135 buf[0] = RD4(sc, TRNG_OUTPUT_L_REG);
136 buf[1] = RD4(sc, TRNG_OUTPUT_H_REG);
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| ti_div_clock.c | 78 #define RD4(sc) \
186 val = RD4(sc);
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| ti_mux_clock.c | 79 #define RD4(sc, reg) \
189 val = RD4(sc, 0);
209 val = RD4(sc, 0);
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| ti_dpll_clock.c | 133 #define RD4(sc, space) \
231 val = RD4(sc, REG_MULT_DIV1);
269 control = RD4(sc, REG_CONTROL);
274 while (RD4(sc, REG_IDLEST) != AM3_ST_MN_BYPASS)
285 while (RD4(sc, REG_IDLEST) != AM3_ST_DPLL_CLK)
309 control = RD4(sc, REG_CONTROL);
324 while ((RD4(sc, REG_IDLEST) & OMAP3_ST_MPU_CLK) != 0)
341 val = RD4(sc, REG_MULT_DIV1);
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| ti_lcdc.h | 122 #define RD4(sc, reg) \
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| ti_omaptimer.c | 106 #define RD4(sc, reg) \
151 return RD4(sc, TIMER_TCRR);
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| ti_usb.c | 123 #define RD4(sc, reg) \
134 val = RD4(sc, UHH_SYSCONFIG);
143 val = RD4(sc, UHH_SYSCONFIG);
145 val = RD4(sc, UHH_HOSTCONFIG);
|
| ti_usbtll.c | 97 #define RD4(sc, reg) \
117 val = RD4(sc, USBTLL_CHANNEL_CONF(port));
133 val = RD4(sc, USBTLL_SYSSTATUS);
155 val = RD4(sc, USBTLL_SHARED_CONF);
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| ti_wdt.c | 88 #define RD4(sc, reg) \
100 val = RD4(sc, WDT_WWPS);
121 val = RD4(sc, WDT_WDSC);
125 val = RD4(sc, WDT_WDSC);
194 val = RD4(sc, WDT_WTGR);
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| /src/sys/arch/evbppc/wii/dev/ |
| hwgpio.c | 83 #define RD4(reg) in32(reg)
89 return (RD4(HW_GPIOB_IN) & __BIT(pin)) != 0;
99 out = RD4(HW_GPIOB_OUT);
116 dir = RD4(HW_GPIOB_DIR);
149 in = RD4(HW_GPIOB_IN);
150 out = RD4(HW_GPIOB_OUT);
151 dir = RD4(HW_GPIOB_DIR);
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| hollywood.c | 48 #define RD4(reg) in32(reg)
96 val = RD4(HW_VERSION);
170 raw = RD4(HW_PPCIRQFLAGS);
192 val = RD4(HW_ARMIRQMASK);
227 WR4(HW_AHBPROT, RD4(HW_AHBPROT) & ~mask);
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| /src/sys/arch/riscv/starfive/ |
| jh7110_syscon.c | 52 #define RD4(sc, reg) \
81 return RD4(sc, reg);
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| jh7110_pciephy.c | 57 #define RD4(sc, reg) \
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| jh71x0_temp.c | 51 #define RD4(sc, reg) \
72 uint32_t temp = RD4(sc, JH71X0_TEMP);
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| /src/sys/arch/arm/sunxi/ |
| sun8i_a23_apbclk.c | 78 #define RD4(sc, reg) \
174 const uint32_t val = RD4(sc, 0);
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| sun9i_a80_cpusclk.c | 80 #define RD4(sc, reg) \
176 const uint32_t val = RD4(sc, 0);
193 const uint32_t val = RD4(sc, 0);
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| sunxi_gmacclk.c | 84 #define RD4(sc, reg) \
179 val = RD4(sc, 0);
212 val = RD4(sc, 0);
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| /src/sys/dev/ic/ |
| dwc_wdt.c | 84 #define RD4(sc, reg) \
144 cr = RD4(sc, WDT_CR);
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| cdnsiic.c | 88 #define RD4(sc, reg) \
148 sr_val = RD4(sc, SR_REG);
149 isr_val = RD4(sc, ISR_REG);
169 val = RD4(sc, ISR_REG);
192 val = RD4(sc, CR_REG);
196 WR4(sc, ISR_REG, RD4(sc, ISR_REG));
199 fifo_space = FIFO_DEPTH - RD4(sc, TRANS_SIZE_REG);
229 val = RD4(sc, CR_REG);
232 WR4(sc, ISR_REG, RD4(sc, ISR_REG));
241 *data = RD4(sc, DATA_REG) & 0xff
[all...] |
| /src/sys/arch/arm/rockchip/ |
| rk3288_iomux.c | 83 #define RD4(reg, off) \
184 val = RD4(reg, reg->pull_reg);
218 val = RD4(reg, reg->drv_reg);
237 val = RD4(reg, reg->mux_reg);
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| rk3328_iomux.c | 133 #define RD4(sc, reg) \
|
| /src/sys/dev/fdt/ |
| dwc3_fdt.c | 90 #define RD4(sc, reg) \
95 WR4((sc), (reg), RD4((sc), (reg)) | (mask))
97 WR4((sc), (reg), RD4((sc), (reg)) & ~(mask))
132 val = RD4(sc, DWC3_GUSB2PHYCFG(0));
160 val = RD4(sc, DWC3_GUSB3PIPECTL(0));
169 val = RD4(sc, DWC3_GUCTL1);
179 val = RD4(sc, DWC3_DCFG);
199 val = RD4(sc, DWC3_GCTL);
319 const uint32_t snpsid = RD4(sc, DWC3_SNPSID);
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| /src/sys/arch/arm/xilinx/ |
| zynq_gpio.c | 78 #define RD4(sc, reg) \
99 dirm = RD4(sc, DIRM_REG(pin));
100 oen = RD4(sc, OEN_REG(pin));
206 data = RD4(sc, DATA_RO_REG(pin));
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| /src/sys/arch/riscv/sifive/ |
| fu540_prci.c | 86 #define RD4(sc, reg) \
120 val = RD4(sc, reg);
164 val = RD4(sc, DDRPLLCFG1);
168 val = RD4(sc, GEMGXLPLLCFG1);
|
