| /src/sys/arch/evbppc/wii/ |
| pic_pi.c | 53 #define WR4(reg, val) out32(reg, val)
60 WR4(PI_INTMR, pic_irqmask & ~pic_actmask);
67 WR4(PI_INTMR, pic_irqmask & ~pic_actmask);
84 WR4(PI_INTMR, pic_irqmask & ~pic_actmask);
93 WR4(PI_INTMR, pic_irqmask & ~pic_actmask);
94 WR4(PI_INTSR, __BIT(irq));
116 WR4(PI_INTMR, 0);
117 WR4(PI_INTSR, ~0U);
|
| /src/sys/arch/arm/ti/ |
| ti_rng.c | 66 #define WR4(sc, reg, val) \
104 WR4(sc, TRNG_CONFIG_REG,
107 WR4(sc, TRNG_CONTROL_REG,
137 WR4(sc, TRNG_INTACK_REG, TRNG_INTACK_READY);
|
| ti_div_clock.c | 80 #define WR4(sc, val) \
|
| ti_mux_clock.c | 81 #define WR4(sc, reg, val) \
212 WR4(sc, 0, val);
|
| ti_dpll_clock.c | 135 #define WR4(sc, space, val) \
272 WR4(sc, REG_CONTROL, control);
279 WR4(sc, REG_MULT_DIV1, mult_div1);
283 WR4(sc, REG_CONTROL, control);
312 WR4(sc, REG_CONTROL, control);
318 WR4(sc, REG_MULT_DIV1, mult_div1);
322 WR4(sc, REG_CONTROL, control);
|
| ti_lcdc.h | 124 #define WR4(sc, reg, val) \
|
| ti_omaptimer.c | 108 #define WR4(sc, reg, val) \
119 WR4(sc, TIMER_TISR, OVF_IT_FLAG);
143 WR4(sc, TIMER_TIER, OVF_EN_FLAG);
158 WR4(sc, TIMER_TLDR, value);
159 WR4(sc, TIMER_TCRR, value);
160 WR4(sc, TIMER_TIER, 0);
161 WR4(sc, TIMER_TCLR, TCLR_ST | TCLR_AR);
|
| ti_usb.c | 125 #define WR4(sc, reg, val) \
141 WR4(sc, UHH_SYSCONFIG, val);
159 WR4(sc, UHH_HOSTCONFIG, val);
|
| ti_usbtll.c | 99 #define WR4(sc, reg, val) \
122 WR4(sc, USBTLL_CHANNEL_CONF(port), val);
131 WR4(sc, USBTLL_SYSCONFIG, USBTLL_SYSCONFIG_SOFTRESET);
153 WR4(sc, USBTLL_SYSCONFIG, val);
159 WR4(sc, USBTLL_SHARED_CONF, val);
|
| ti_wdt.c | 90 #define WR4(sc, reg, val) \
123 WR4(sc, WDT_WDSC, val);
137 WR4(sc, WDT_WSPR, 0xaaaa);
139 WR4(sc, WDT_WSPR, 0x5555);
146 WR4(sc, WDT_WSPR, 0xbbbb);
148 WR4(sc, WDT_WSPR, 0x4444);
176 WR4(sc, WDT_WCLR, WCLR_PRE | __SHIFTIN(1, WCLR_PTV));
177 WR4(sc, WDT_WLDR, counter_val);
178 WR4(sc, WDT_WCRR, counter_val);
195 WR4(sc, WDT_WTGR, ~val)
[all...] |
| /src/sys/arch/evbppc/wii/dev/ |
| hwgpio.c | 84 #define WR4(reg, val) out32((reg), (val))
105 WR4(HW_GPIOB_OUT, out);
122 WR4(HW_GPIOB_DIR, dir);
|
| hollywood.c | 47 #define WR4(reg, val) out32(reg, val)
154 WR4(HW_PPCIRQMASK, pic_irqmask);
161 WR4(HW_PPCIRQMASK, pic_irqmask);
183 WR4(HW_PPCIRQFLAGS, __BIT(irq));
194 WR4(HW_ARMIRQMASK, val);
195 WR4(HW_ARMIRQFLAGS, __BIT(irq));
204 WR4(HW_PPCIRQMASK, 0);
205 WR4(HW_PPCIRQFLAGS, ~0U);
227 WR4(HW_AHBPROT, RD4(HW_AHBPROT) & ~mask);
|
| avenc.c | 60 #define WR4 avenc_write_4
212 WR4(tag, addr, 0x7a, 0);
218 WR4(tag, addr, 0x7a, 0);
|
| /src/sys/arch/riscv/starfive/ |
| jh7110_syscon.c | 54 #define WR4(sc, reg, val) \
91 WR4(sc, reg, val);
|
| jh7110_pciephy.c | 59 #define WR4(sc, reg, val) \
137 WR4(sc, PCIE_KVCO_LEVEL, PCEI_PHY_KVCO_FINE_TUNE_LEVEL);
138 WR4(sc, PCIE_KVCO_TUNE_SIGNAL, PCIE_KVO_FINE_TUNE_SIGNALS);
|
| jh71x0_temp.c | 53 #define WR4(sc, reg, val) \
92 WR4(sc, JH71X0_TEMP, JH71X0_TEMP_PD);
96 WR4(sc, JH71X0_TEMP, 0);
100 WR4(sc, JH71X0_TEMP, JH71X0_TEMP_RSTN);
104 WR4(sc, JH71X0_TEMP, JH71X0_TEMP_RSTN | JH71X0_TEMP_RUN);
|
| /src/sys/arch/arm/sunxi/ |
| sun8i_a23_apbclk.c | 80 #define WR4(sc, reg, val) \
|
| sun9i_a80_cpusclk.c | 82 #define WR4(sc, reg, val) \
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| sunxi_gmacclk.c | 86 #define WR4(sc, reg, val) \
192 WR4(sc, 0, val);
|
| /src/sys/dev/ic/ |
| dwc_wdt.c | 86 #define WR4(sc, reg, val) \
116 WR4(sc, WDT_CRR, crr);
142 WR4(sc, WDT_TORR, torr);
147 WR4(sc, WDT_CR, cr);
|
| cdnsiic.c | 90 #define WR4(sc, reg, val) \
129 WR4(sc, CR_REG,
136 WR4(sc, TIME_OUT_REG, 0xff);
195 WR4(sc, CR_REG, val);
196 WR4(sc, ISR_REG, RD4(sc, ISR_REG));
202 WR4(sc, DATA_REG, *data);
205 WR4(sc, ADDR_REG, addr);
231 WR4(sc, CR_REG, val);
232 WR4(sc, ISR_REG, RD4(sc, ISR_REG));
233 WR4(sc, TRANS_SIZE_REG, datalen)
[all...] |
| /src/sys/arch/arm/rockchip/ |
| rk3288_iomux.c | 85 #define WR4(reg, off, val) \
190 WR4(reg, reg->pull_reg, val);
224 WR4(reg, reg->drv_reg, val);
243 WR4(reg, reg->mux_reg, val);
|
| rk3328_iomux.c | 135 #define WR4(sc, reg, val) \
166 WR4(sc, GRF_GPIO_P_REG(bank, idx),
174 WR4(sc, GRF_GPIO_E_REG(bank, idx),
187 WR4(sc, reg, (mask << 16) | __SHIFTIN(mux, mask));
|
| /src/sys/dev/fdt/ |
| dwc3_fdt.c | 92 #define WR4(sc, reg, val) \
95 WR4((sc), (reg), RD4((sc), (reg)) | (mask))
97 WR4((sc), (reg), RD4((sc), (reg)) & ~(mask))
158 WR4(sc, DWC3_GUSB2PHYCFG(0), val);
166 WR4(sc, DWC3_GUSB3PIPECTL(0), val);
172 WR4(sc, DWC3_GUCTL1, val);
191 WR4(sc, DWC3_DCFG, val);
202 WR4(sc, DWC3_GCTL, val);
|
| /src/sys/arch/arm/xilinx/ |
| zynq_gpio.c | 80 #define WR4(sc, reg, val) \
108 WR4(sc, OEN_REG(pin), oen);
109 WR4(sc, DIRM_REG(pin), dirm);
224 WR4(sc, MASK_DATA_REG(pin), mask_data);
|
