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  /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/gr/
nouveau_nvkm_engine_gr_tu102.c 64 u8 bank[GPC_MAX] = {}, gpc, i, j; local
69 data |= bank[gr->tile[i + j]] << (j * 4);
70 bank[gr->tile[i + j]]++;
nouveau_nvkm_engine_gr_gf117.c 136 u8 bank[GPC_MAX] = {}, gpc, i, j; local
141 data |= bank[gr->tile[i + j]] << (j * 4);
142 bank[gr->tile[i + j]]++;
  /src/games/trek/
phaser.c 62 ** direction you want each bank to be aimed, the number
108 struct banks bank[NBANKS]; local
154 /* initialize the bank[] array */
157 bank[i].units = 0;
165 b = &bank[i];
218 b = &bank[i];
249 b = &bank[i];
270 b = &bank[i];
283 b = &bank[i];
287 printf("\nPhaser bank %d fires:\n", i)
    [all...]
  /src/sys/arch/amiga/dev/
gtscreg.h 56 vu_short bank; member in struct:sdmac
  /src/sys/arch/arm/amlogic/
meson_pinctrl.h 64 u_int bank[MESON_PINCTRL_MAXBANK]; member in struct:meson_pinctrl_group
  /src/sys/arch/arm/samsung/
exynos_pinctrl.c 166 struct exynos_gpio_bank *bank; local
177 bank = exynos_gpio_bank_lookup(epb, pins);
179 if (bank == NULL) {
184 exynos_gpio_pin_ctl_write(bank, gc, pin);
exynos_gpio.c 241 #define GPIO_WRITE(bank, reg, val) \
242 bus_space_write_4((bank)->bank_sc->sc_bst, \
243 (bank)->bank_sc->sc_bsh, \
244 (bank)->bank_core_offset + (reg), (val))
245 #define GPIO_READ(bank, reg) \
246 bus_space_read_4((bank)->bank_sc->sc_bst, \
247 (bank)->bank_sc->sc_bsh, \
248 (bank)->bank_core_offset + (reg))
254 struct exynos_gpio_bank *bank = gba->gba_gc->gp_cookie; local
255 const char *bankname = bank->bank_name
268 struct exynos_gpio_bank * const bank = cookie; local
281 struct exynos_gpio_bank * const bank = cookie; local
297 struct exynos_gpio_bank * const bank = cookie; local
375 struct exynos_gpio_bank *bank = local
423 struct exynos_gpio_bank *bank; local
456 struct exynos_gpio_bank *bank = NULL; local
    [all...]
  /src/external/gpl3/binutils/dist/bfd/
coff-tic4x.c 173 int bank = (dst->r_symndx == -1) ? HOWTO_BANK : 0; local
179 internal->howto = tic4x_howto_table + i + bank;
coff-tic54x.c 138 /* NORMAL BANK */
164 /* ABSOLUTE BANK */
251 int bank = (dst->r_symndx == -1) ? HOWTO_BANK : 0; local
257 internal->howto = tic54x_howto_table + i + bank;
  /src/external/gpl3/binutils.old/dist/bfd/
coff-tic4x.c 173 int bank = (dst->r_symndx == -1) ? HOWTO_BANK : 0; local
179 internal->howto = tic4x_howto_table + i + bank;
coff-tic54x.c 138 /* NORMAL BANK */
164 /* ABSOLUTE BANK */
251 int bank = (dst->r_symndx == -1) ? HOWTO_BANK : 0; local
257 internal->howto = tic54x_howto_table + i + bank;
  /src/external/gpl3/gdb/dist/bfd/
coff-tic4x.c 173 int bank = (dst->r_symndx == -1) ? HOWTO_BANK : 0; local
179 internal->howto = tic4x_howto_table + i + bank;
coff-tic54x.c 138 /* NORMAL BANK */
164 /* ABSOLUTE BANK */
251 int bank = (dst->r_symndx == -1) ? HOWTO_BANK : 0; local
257 internal->howto = tic54x_howto_table + i + bank;
  /src/external/gpl3/gdb.old/dist/bfd/
coff-tic4x.c 173 int bank = (dst->r_symndx == -1) ? HOWTO_BANK : 0; local
179 internal->howto = tic4x_howto_table + i + bank;
coff-tic54x.c 138 /* NORMAL BANK */
164 /* ABSOLUTE BANK */
251 int bank = (dst->r_symndx == -1) ? HOWTO_BANK : 0; local
257 internal->howto = tic54x_howto_table + i + bank;
  /src/sys/dev/ic/
mcp23xxxgpio.c 65 mcpgpio_regaddr(struct mcpgpio_softc *sc, uint8_t bank, uint8_t reg)
72 return REGADDR_BANK1(bank & 1, reg);
74 return REGADDR_BANK0(bank & 1, reg);
98 mcpgpio_bankname(struct mcpgpio_softc *sc, uint8_t bank)
105 return banknames[bank & 1];
132 uint8_t bank, uint8_t reg, uint8_t *valp)
135 uint8_t regaddr = mcpgpio_regaddr(sc, bank, reg);
137 error = sc->sc_accessops->read(sc, bank, regaddr, valp);
141 mcpgpio_regname(reg), mcpgpio_bankname(sc, bank),
152 uint8_t bank, uint8_t reg, uint8_t val
182 const uint8_t bank = PIN_BANK(pin); local
209 const uint8_t bank = PIN_BANK(pin); local
239 const uint8_t bank = PIN_BANK(pin); local
    [all...]
ug.c 349 uint8_t bank, sens, rv; local
351 bank = (sensor & 0xFF00) >> 8;
354 bus_space_write_1(sc->sc_iot, sc->sc_ioh, UG_DATA, bank);
638 ug2_read(struct ug_softc *sc, uint8_t bank, uint8_t offset, uint8_t count,
650 bus_space_write_1(iot, ioh, UG_CMD, bank);
  /src/sys/dev/mvme/
memc.c 95 MEMECC_SYN_BANK_C | 10, /* 0x07: Bank C 10/26 */
99 MEMECC_SYN_BANK_C | 13, /* 0x0b: Bank C 13/29 */
101 MEMECC_SYN_BANK_D | 1, /* 0x0d: Bank D 1/17 */
102 MEMECC_SYN_BANK_D | 2, /* 0x0e: Bank D 2/18 */
107 MEMECC_SYN_BANK_C | 14, /* 0x13: Bank C 14/30 */
109 MEMECC_SYN_BANK_D | 4, /* 0x15: Bank D 4/20 */
110 MEMECC_SYN_BANK_D | 5, /* 0x16: Bank D 5/21 */
113 MEMECC_SYN_BANK_D | 8, /* 0x19: Bank D 8/24 */
114 MEMECC_SYN_BANK_D | 9, /* 0x1a: Bank D 9/25 */
116 MEMECC_SYN_BANK_D | 10, /* 0x1c: Bank D 10/26 *
572 int syncode, bank, bitnum; local
    [all...]
  /src/sys/dev/spi/
mcp23xxxgpio_spi.c 138 mcpgpio_spi_read(struct mcpgpio_softc *sc, unsigned int bank,
144 KASSERT(bank < (sc->sc_npins >> 3));
146 buf[0] = OP_READ(ssc->sc_ha[bank]);
153 mcpgpio_spi_write(struct mcpgpio_softc *sc, unsigned int bank,
159 KASSERT(bank < (sc->sc_npins >> 3));
161 buf[0] = OP_WRITE(ssc->sc_ha[bank]);
241 int bank, nchips, error, ha; local
266 * XXX Going on blind faith that IOCON.BANK is already 0.
321 /* Record the hardware addresses for each logical bank of 8 pins. */
322 for (bank = 0; spi_present_mask != 0; spi_present_mask &= ~__BIT(ha))
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_ras_eeprom.h 75 unsigned char bank; member in union:eeprom_table_record::__anon4310
  /src/sys/arch/arm/nvidia/
tegra_gpio.c 139 #define GPIO_WRITE(bank, reg, val) \
140 bus_space_write_4((bank)->bank_sc->sc_bst, \
141 (bank)->bank_sc->sc_bsh, \
142 (bank)->bank_pb->base + (reg), (val))
143 #define GPIO_READ(bank, reg) \
144 bus_space_read_4((bank)->bank_sc->sc_bst, \
145 (bank)->bank_sc->sc_bsh, \
146 (bank)->bank_pb->base + (reg))
202 struct tegra_gpio_bank *bank = &sc->sc_banks[bankno]; local
206 bank->bank_sc = sc
240 struct tegra_gpio_bank *bank = gba->gba_gc->gp_cookie; local
254 struct tegra_gpio_bank *bank = priv; local
264 struct tegra_gpio_bank *bank = priv; local
275 struct tegra_gpio_bank *bank = priv; local
298 const u_int bank = be32toh(gpio[1]) >> 3; local
389 struct tegra_gpio_bank bank; local
    [all...]
  /src/sys/arch/arm/rockchip/
rk3288_iomux.c 126 rk3288_iomux_get_reg(struct rk3288_iomux_softc *sc, u_int bank, u_int idx,
129 if (bank >= NBANKS || idx >= NPINSPERBANK) {
133 if (bank == 0) {
141 reg->pull_reg = 0x130 + (bank * 0x10) + (idx / 8) * 4;
143 reg->drv_reg = 0x1b0 + (bank * 0x10) + (idx / 8) * 4;
146 reg->flags = rk3288_iomux_flags[bank][idx / 8];
147 reg->mux_reg = rk3288_iomux_offset[bank][idx / 8];
294 const u_int bank = be32toh(pins[0]); local
300 if (rk3288_iomux_get_reg(sc, bank, idx, &regdef)) {
302 printf(" -> gpio%u P%c%u (%u)\n", bank, 'A' + (idx / 8), idx % 8, idx)
    [all...]
rk3328_iomux.c 145 rk3328_iomux_calc_iomux_reg(struct rk3328_iomux_softc *sc, u_int bank, u_int pin, bus_size_t *reg, uint32_t *mask)
149 KASSERT(bank < sc->sc_conf->nbanks);
151 *reg = banks[bank].iomux[pin / 8].base;
152 if (banks[bank].iomux[pin / 8].type & RK3328_IOMUX_TYPE_3BIT) {
164 rk3328_iomux_set_bias(struct rk3328_iomux_softc *sc, u_int bank, u_int idx, u_int bias)
166 WR4(sc, GRF_GPIO_P_REG(bank, idx),
172 rk3328_iomux_set_drive_strength(struct rk3328_iomux_softc *sc, u_int bank, u_int idx, u_int drv)
174 WR4(sc, GRF_GPIO_E_REG(bank, idx),
180 rk3328_iomux_set_mux(struct rk3328_iomux_softc *sc, u_int bank, u_int idx, u_int mux)
185 rk3328_iomux_calc_iomux_reg(sc, bank, idx, &reg, &mask)
256 const u_int bank = be32toh(pins[0]); local
    [all...]
rk3588_iomux.c 70 #define PIN(bank, idx) (((bank) * NPINPERBANK) + (idx))
844 int bank = pin / 32; local
848 pin, bank, 'A' + group, idx);
942 u_int bank, u_int idx, u_int mux)
944 const int pin = PIN(bank, idx);
981 const u_int bank = be32toh(pins[0]); local
988 rk3588_iomux_config(sc, cfg, bank, idx, mux);
  /src/sys/arch/hpc/stand/hpcboot/
memory.h 55 struct bank { struct in class:MemoryManager
71 // Pagesize, D-RAM bank
75 struct bank _bank[MAX_MEM_BANK];

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