| /src/sys/arch/arm/amlogic/ |
| H A D | meson_clk_div.c | 85 int parent_rate; local in function:meson_clk_div_set_rate
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| H A D | meson_clk_mpll.c | 47 uint64_t parent_rate, sdm, n2; local in function:meson_clk_mpll_get_rate
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| H A D | meson_clk_pll.c | 46 uint64_t parent_rate, rate; local in function:meson_clk_pll_get_rate
104 uint64_t parent_rate, tmp; local in function:meson_clk_pll_set_rate
[all...] |
| H A D | meson8b_clkc.c | 116 const u_int parent_rate = clk_get_rate(clkp_parent); local in function:meson8b_clkc_pll_sys_set_rate
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| H A D | mesongx_mmc.c | 482 const u_int parent_rate = clk_get_rate(sc->sc_clk_clkin[sel]); local in function:mesongx_mmc_set_clock
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| /src/sys/arch/arm/rockchip/ |
| H A D | rk_cru_arm.c | 96 const u_int parent_rate = arm_rate->rate / arm_rate->div; local in function:rk_cru_arm_set_rate_rates
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| /src/sys/arch/arm/sunxi/ |
| H A D | sunxi_ccu_display.c | 105 int parent_rate, best_parent_rate = 0; local in function:sunxi_ccu_lcdxch1_set_rate
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| H A D | sunxi_ccu_div.c | 139 int parent_rate; local in function:sunxi_ccu_div_set_rate
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| H A D | sunxi_ccu_fractional.c | 110 u_int parent_rate, best_rate, best_m; local in function:sunxi_ccu_fractional_set_rate
189 u_int parent_rate, best_rate; local in function:sunxi_ccu_fractional_round_rate
[all...] |
| H A D | sunxi_ccu_nm.c | 107 u_int parent_rate, best_rate, best_n, best_m, best_parent; local in function:sunxi_ccu_nm_set_rate
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| H A D | sunxi_twi.c | 85 sunxi_twi_calc_rate(u_int parent_rate, u_int n, u_int m) argument
91 sunxi_twi_set_clock(struct gttwsi_softc *sc, u_int parent_rate, u_int rate) argument
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| H A D | sunxi_hdmi.c | 848 int parent_rate; local in function:sunxi_hdmi_set_videomode
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| H A D | sunxi_hdmiphy.c | 374 const u_int parent_rate = clk_get_rate(sc->sc_clk_pll0); local in function:sunxi_hdmiphy_set_rate
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| H A D | sunxi_rtc.c | 525 u_int parent_rate = clk_get_rate(sc->sc_parent_clk); local in function:sunxi_rtc_clk_get_rate
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| /src/sys/arch/arm/ti/ |
| H A D | ti_div_clock.c | 158 uint64_t parent_rate; local in function:ti_div_clock_get_rate
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| H A D | ti_dpll_clock.c | 226 uint64_t parent_rate; local in function:ti_dpll_clock_get_rate
254 uint64_t parent_rate; local in function:am3_dpll_clock_set_rate
296 uint64_t parent_rate; local in function:omap3_dpll_clock_set_rate
336 uint64_t parent_rate; local in function:omap3_dpll_core_clock_get_rate
[all...] |
| /src/sys/arch/riscv/starfive/ |
| H A D | jh71x0_clkc.c | 253 u_int parent_rate = clk_get_rate(clk_parent); local in function:jh71x0_clkc_div_set_rate
442 u_int parent_rate = clk_get_rate(clk_parent); local in function:jh71x0_clkc_muxdiv_set_rate
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| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/clk/ |
| H A D | gk20a.h | 122 u32 parent_rate; member in struct:gk20a_clk
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| H A D | nouveau_nvkm_subdev_clk_gm20b.c | 496 u32 parent_rate = clk->base.parent_rate / KHZ; local in function:gm20b_dvfs_calc_safe_pll
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| /src/sys/arch/arm/altera/ |
| H A D | cycv_clkmgr.c | 457 uint32_t parent_rate = 0; local in function:cycv_clkmgr_clock_get_rate
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| /src/sys/arch/arm/samsung/ |
| H A D | exynos5410_clock.c | 655 const u_int parent_rate = exynos5410_clock_get_rate(sc, clk_parent); local in function:exynos5410_clock_get_rate_div
675 const u_int parent_rate = exynos5410_clock_get_rate(sc, clk_parent); local in function:exynos5410_clock_set_rate_div
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| H A D | exynos5422_clock.c | 832 const u_int parent_rate = exynos5422_clock_get_rate(sc, clk_parent); local in function:exynos5422_clock_get_rate_div
852 const u_int parent_rate = exynos5422_clock_get_rate(sc, clk_parent); local in function:exynos5422_clock_set_rate_div
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| /src/sys/arch/arm/nvidia/ |
| H A D | tegra124_car.c | 1216 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent); local in function:tegra124_car_clock_get_rate_fixed_div
1244 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent); local in function:tegra124_car_clock_get_rate_div
1294 const u_int parent_rate = tegra124_car_clock_get_rate(sc, clk_parent); local in function:tegra124_car_clock_set_rate_div
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| H A D | tegra210_car.c | 1322 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); local in function:tegra210_car_clock_get_rate_fixed_div
1340 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); local in function:tegra210_car_clock_get_rate_div
1398 const u_int parent_rate = tegra210_car_clock_get_rate(sc, clk_parent); local in function:tegra210_car_clock_set_rate_div
[all...] |
| H A D | tegra_drm_mode.c | 638 const u_int parent_rate = clk_get_rate(tegra_crtc->clk_parent); local in function:tegra_crtc_mode_set
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