| /src/sys/arch/arm/xscale/ |
| ixp425_pci_space.c | 51 #define CSR_READ_4(x) *(volatile uint32_t *) \
272 data = CSR_READ_4(PCI_NP_RDATA);
273 if (CSR_READ_4(PCI_ISR) & ISR_PFE)
292 data = CSR_READ_4(PCI_NP_RDATA);
293 if (CSR_READ_4(PCI_ISR) & ISR_PFE)
309 data = CSR_READ_4(PCI_NP_RDATA);
310 if (CSR_READ_4(PCI_ISR) & ISR_PFE)
332 if (CSR_READ_4(PCI_ISR) & ISR_PFE)
352 if (CSR_READ_4(PCI_ISR) & ISR_PFE)
367 if (CSR_READ_4(PCI_ISR) & ISR_PFE
[all...] |
| pxa2x0_mci.c | 149 #define CSR_READ_4(sc, reg) \
154 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (val))
156 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(val))
732 if (ISSET(CSR_READ_4(sc, MMC_STAT), STAT_CLK_EN)) {
735 while (ISSET(CSR_READ_4(sc, MMC_STAT), STAT_CLK_EN)
757 status = CSR_READ_4(sc, MMC_I_REG) & ~CSR_READ_4(sc, MMC_I_MASK);
884 uint32_t h = CSR_READ_4(sc, MMC_RES) & 0xffff;
885 uint32_t l = CSR_READ_4(sc, MMC_RES) & 0xffff;
907 uint32_t h = CSR_READ_4(sc, MMC_RES) & 0xffff
[all...] |
| pxa2x0_i2c.c | 407 #define CSR_READ_4(sc,r) bus_space_read_4(sc->sc_iot, sc->sc_ioh, r)
423 while (CSR_READ_4(sc, I2C_ICR) & ~ICR_UR)
436 isr = CSR_READ_4(sc, I2C_ISR);
512 *bytep = CSR_READ_4(sc, I2C_IDBR);
|
| /src/sys/dev/pci/ |
| if_bgevar.h | 103 #define CSR_READ_4(sc, reg) \
109 CSR_READ_4(sc, reg); \
113 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))
117 CSR_READ_4(sc, reg); \
120 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
124 CSR_READ_4(sc, reg); \
|
| if_bge.c | 955 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
963 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
970 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
982 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
1046 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
1056 byte = CSR_READ_4(sc, BGE_EE_DATA);
1098 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
1110 data = CSR_READ_4(sc, BGE_MI_COMM);
1113 data = CSR_READ_4(sc, BGE_MI_COMM);
1157 autopoll = CSR_READ_4(sc, BGE_MI_MODE)
[all...] |
| if_alc.c | 222 v = CSR_READ_4(sc, ALC_MDIO);
254 v = CSR_READ_4(sc, ALC_MDIO);
294 v = CSR_READ_4(sc, ALC_MDIO);
323 v = CSR_READ_4(sc, ALC_MDIO);
371 reg = CSR_READ_4(sc, ALC_MAC_CFG);
425 v = CSR_READ_4(sc, ALC_MDIO);
457 v = CSR_READ_4(sc, ALC_MDIO);
619 opt = CSR_READ_4(sc, ALC_OPT_CFG);
620 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 &&
621 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0)
[all...] |
| if_age.c | 214 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >>
222 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN),
223 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN));
362 v = CSR_READ_4(sc, AGE_MDIO);
396 v = CSR_READ_4(sc, AGE_MDIO);
444 reg = CSR_READ_4(sc, AGE_MAC_CFG);
446 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) |
496 status = CSR_READ_4(sc, AGE_INTR_STATUS);
567 reg = CSR_READ_4(sc, AGE_SPI_CTRL);
580 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL)
[all...] |
| if_ale.c | 155 v = CSR_READ_4(sc, ALE_MDIO);
196 v = CSR_READ_4(sc, ALE_MDIO);
246 reg = CSR_READ_4(sc, ALE_MAC_CFG);
296 reg = CSR_READ_4(sc, ALE_SPI_CTRL);
308 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
312 reg = CSR_READ_4(sc, ALE_TWSI_CTRL);
325 ea[0] = CSR_READ_4(sc, ALE_PAR0);
326 ea[1] = CSR_READ_4(sc, ALE_PAR1);
461 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) {
493 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >
[all...] |
| if_stge.c | 230 #define CSR_READ_4(_sc, reg) \
565 if (CSR_READ_4(sc, STGE_AsicCtrl) & AC_PhyMedia)
792 if ((CSR_READ_4(sc, STGE_DMACtrl) & DMAC_TxDMAInProg) == 0)
1137 txstat = CSR_READ_4(sc, STGE_TxStatus);
1430 (void) CSR_READ_4(sc, STGE_OctetRcvOk);
1432 (void) CSR_READ_4(sc, STGE_FramesRcvdOk);
1439 (void) CSR_READ_4(sc, STGE_OctetXmtdOk);
1442 CSR_READ_4(sc, STGE_FramesXmtdOk));
1445 CSR_READ_4(sc, STGE_LateCollisions) +
1446 CSR_READ_4(sc, STGE_MultiColFrames)
[all...] |
| if_ipw.c | 146 return CSR_READ_4(sc, IPW_CSR_INDIRECT_DATA);
1118 r = CSR_READ_4(sc, IPW_CSR_RX_READ);
1227 r = CSR_READ_4(sc, IPW_CSR_TX_READ);
1255 r = CSR_READ_4(sc, IPW_CSR_INTR);
1273 r = CSR_READ_4(sc, IPW_CSR_INTR);
1595 size = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA);
1600 addr = CSR_READ_4(sc, IPW_CSR_AUTOINC_DATA);
1619 else if (CSR_READ_4(sc, IPW_CSR_IO) & IPW_IO_RADIO_DISABLED)
1747 if (CSR_READ_4(sc, IPW_CSR_RST) & IPW_RST_MASTER_DISABLED)
1754 CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST)
[all...] |
| if_ti.c | 244 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
268 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
277 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
285 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
296 device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
307 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
1155 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1225 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1229 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1267 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL)
[all...] |
| if_iwi.c | 161 return CSR_READ_4(sc, IWI_CSR_INDIRECT_DATA);
887 rate = iwi_cvtrate(CSR_READ_4(sc, IWI_CSR_CURRENT_TX_RATE));
1370 (void)CSR_READ_4(sc, IWI_CSR_CMD_RIDX);
1393 hw = CSR_READ_4(sc, IWI_CSR_RX_RIDX);
1442 hw = CSR_READ_4(sc, txq->csr_ridx);
1481 if ((r = CSR_READ_4(sc, IWI_CSR_INTR)) == 0 || r == 0xffffffff)
1498 if ((r = CSR_READ_4(sc, IWI_CSR_INTR)) == 0 || r == 0xffffffff)
1868 size = uimin(CSR_READ_4(sc, IWI_CSR_TABLE0_SIZE), 128 - 1);
1958 if (CSR_READ_4(sc, IWI_CSR_RST) & IWI_RST_MASTER_DISABLED)
1965 CSR_WRITE_4(sc, IWI_CSR_RST, CSR_READ_4(sc, IWI_CSR_RST)
[all...] |
| if_et.c | 380 data = CSR_READ_4(sc, ET_MII_IND);
394 data = CSR_READ_4(sc, ET_MII_STAT);
426 data = CSR_READ_4(sc, ET_MII_IND);
474 ctrl = CSR_READ_4(sc, ET_MAC_CTRL);
476 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1);
479 cfg2 = CSR_READ_4(sc, ET_MAC_CFG2);
523 cfg1 = CSR_READ_4(sc, ET_MAC_CFG1);
1023 intrs = CSR_READ_4(sc, ET_INTR_STATUS);
1211 if ((CSR_READ_4(sc, ET_RXDMA_CTRL) & ET_RXDMA_CTRL_HALTED) == 0) {
1286 pktfilt = CSR_READ_4(sc, ET_PKTFILT)
[all...] |
| if_ipwreg.h | 319 #define CSR_READ_4(sc, reg) \
|
| if_tireg.h | 39 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
966 #define CSR_READ_4(sc, reg) \
972 #define CSR_READ_4(sc, reg) \
977 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))
979 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
|
| /src/sys/arch/sandpoint/stand/altboot/ |
| pcn.c | 47 #define CSR_READ_4(l, r) in32rb((l)->csr+(r))
157 (void)CSR_READ_4(l, PCN_32RESET);
314 return CSR_READ_4(l, PCN_RDP);
328 return CSR_READ_4(l, PCN_BDP);
|
| siisata.c | 41 #define CSR_READ_4(r) in32rb(r)
184 val = CSR_READ_4(ss); /* has completed */
|
| rge.c | 52 #define CSR_READ_4(l, r) in32rb((l)->csr+(r))
323 v = CSR_READ_4(l, RGE_PHYAR);
338 v = CSR_READ_4(l, RGE_PHYAR);
|
| stg.c | 46 #define CSR_READ_4(l, r) in32rb((l)->csr+(r))
363 reg = CSR_READ_4(l, STGE_AsicCtrl);
370 if ((CSR_READ_4(l, STGE_AsicCtrl) & AC_ResetBusy) == 0)
|
| fxp.c | 94 #define CSR_READ_4(l, r) in32rb((l)->iobase+(r))
520 while (((value = CSR_READ_4(sc, FXP_CSR_MDICONTROL)) &
|
| /src/sys/dev/ic/ |
| wivar.h | 240 #define CSR_READ_4(sc, reg) \
262 #define CSR_READ_4(sc, reg) \
|
| bwi.c | 734 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
742 intr_mask = CSR_READ_4(sc, BWI_MAC_INTR_MASK);
766 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
809 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8)
1242 return (CSR_READ_4(sc, BWI_MOBJ_DATA));
1290 CSR_READ_4(mac->mac_sc, BWI_STATE_HI); /* dummy read */
1516 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
1522 CSR_READ_4(sc, BWI_STATE_LO);
1528 CSR_READ_4(sc, BWI_STATE_LO);
1533 status = CSR_READ_4(sc, BWI_MAC_STATUS)
[all...] |
| rtl81x9var.h | 285 #define CSR_READ_4(sc, reg) \
|
| bwivar.h | 80 #define CSR_READ_4(sc, reg) \
95 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))
100 CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits))
105 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))
|
| /src/sys/arch/evbarm/ixm1200/ |
| nappi_nppb.c | 62 #define CSR_READ_4(sc, reg) \
|
