| /src/sys/arch/evbppc/nintendo/dev/ |
| gecko.c | 67 #define WR4(reg, val) out32(EXI_BASE + (reg), val)
123 WR4(EXI_CSR(usbgecko_chan), USBGECKO_CSR);
124 WR4(EXI_DATA(usbgecko_chan), command32);
125 WR4(EXI_CR(usbgecko_chan), USBGECKO_CR(2, EXI_CR_RW_READWRITE));
128 WR4(EXI_CSR(usbgecko_chan), 0);
141 WR4(EXI_CSR(usbgecko_chan), USBGECKO_CSR);
142 WR4(EXI_DATA(usbgecko_chan), 0);
143 WR4(EXI_CR(usbgecko_chan), USBGECKO_CR(2, EXI_CR_RW_READWRITE));
145 WR4(EXI_CR(usbgecko_chan), USBGECKO_CR(sizeof(value),
149 WR4(EXI_CSR(usbgecko_chan), 0)
[all...] |
| ahb.c | 48 #define WR4(reg, val) out32(reg, val)
179 WR4(HW_PPCIRQMASK, pic_irqmask[0]);
186 WR4(HW_PPCIRQMASK, pic_irqmask[0]);
208 WR4(HW_PPCIRQFLAGS, __BIT(irq));
219 WR4(HW_ARMIRQMASK, val);
220 WR4(HW_ARMIRQFLAGS, __BIT(irq));
229 WR4(reg_en, pic_irqmask[irq / 32]);
238 WR4(reg_en, pic_irqmask[irq / 32]);
268 WR4(reg_sts, __BIT(irq % 32));
281 WR4(reg_en, val)
[all...] |
| di.c | 140 #define WR4(sc, reg, val) \
263 WR4(sc, DICMDBUF0, DI_CMD_REQUEST_ERROR);
264 WR4(sc, DICMDBUF1, 0);
265 WR4(sc, DICMDBUF2, 0);
266 WR4(sc, DILENGTH, 4);
267 WR4(sc, DICR, DICR_TSTART);
411 WR4(sc, DISR, sr);
412 WR4(sc, DICVR, cvr);
466 WR4(sc, DISR, DISR_BRKINT |
469 WR4(sc, DICVR, DICVR_CVRINT | DICVR_CVRINTMASK)
[all...] |
| wiifb.c | 162 #define WR4(sc, reg, val) \
272 WR4(sc, VI_DI0, VI_DI_ENB |
275 WR4(sc, VI_DI1, 0);
276 WR4(sc, VI_DI2, 0);
277 WR4(sc, VI_DI3, 0);
678 WR4(sc, VI_DI0, RD4(sc, VI_DI0) & ~VI_DI_INT);
679 WR4(sc, VI_DI1, RD4(sc, VI_DI1) & ~VI_DI_INT);
680 WR4(sc, VI_DI2, RD4(sc, VI_DI2) & ~VI_DI_INT);
681 WR4(sc, VI_DI3, RD4(sc, VI_DI3) & ~VI_DI_INT);
729 WR4(sc, VI_HTR0, 0x476901AD)
[all...] |
| ahcisata_ahb.c | 54 #define WR4(sc, reg, val) \
75 WR4(sc, SATA_HCCFG_INT_REG, val);
108 WR4(sc, SATA_HCCFG_INT_REG, ~0U);
109 WR4(sc, SATA_HCCFG_INTMSK_REG, SATA_HCCFG_INT_PORT0 |
|
| exi.c | 79 #define WR4(sc, reg, val) \
214 WR4(exi_softc, EXI_CSR(chan), val);
229 WR4(exi_softc, EXI_CSR(chan), val);
271 WR4(exi_softc, EXI_DATA(chan), val);
272 WR4(exi_softc, EXI_CR(chan),
291 WR4(exi_softc, EXI_CR(chan),
336 WR4(exi_softc, EXI_DATA(chan), val);
337 WR4(exi_softc, EXI_CR(chan),
383 WR4(exi_softc, EXI_MAR(chan), ch->ch_dmamap->dm_segs[0].ds_addr);
384 WR4(exi_softc, EXI_LENGTH(chan), datalen)
[all...] |
| bwai.c | 86 #define WR4(sc, reg, val) \
98 WR4(sc, AI_AIIT, sc->sc_intrnext);
99 WR4(sc, AI_CONTROL, val);
221 WR4(sc, AI_CONTROL, 0);
226 WR4(sc, AI_AIIT, sc->sc_intrnext);
232 WR4(sc, AI_CONTROL, val);
235 WR4(sc, AI_CONTROL, val);
245 WR4(sc, AI_CONTROL, 0);
|
| /src/sys/dev/ic/ |
| bcmgenet.c | 89 #define WR4(sc, reg, val) \
98 WR4(sc, GENET_MDIO_CMD,
125 WR4(sc, GENET_MDIO_CMD,
167 WR4(sc, GENET_EXT_RGMII_OOB_CTRL, val);
172 WR4(sc, GENET_UMAC_CMD, val);
191 WR4(sc, GENET_TX_DESC_ADDRESS_LO(index), BUS_ADDR_LO32(paddr));
192 WR4(sc, GENET_TX_DESC_ADDRESS_HI(index), BUS_ADDR_HI32(paddr));
193 WR4(sc, GENET_TX_DESC_STATUS(index), status);
261 WR4(sc, GENET_RX_DESC_ADDRESS_LO(index), BUS_ADDR_LO32(paddr));
262 WR4(sc, GENET_RX_DESC_ADDRESS_HI(index), BUS_ADDR_HI32(paddr))
[all...] |
| cdnsiic.c | 90 #define WR4(sc, reg, val) \
129 WR4(sc, CR_REG,
136 WR4(sc, TIME_OUT_REG, 0xff);
195 WR4(sc, CR_REG, val);
196 WR4(sc, ISR_REG, RD4(sc, ISR_REG));
202 WR4(sc, DATA_REG, *data);
205 WR4(sc, ADDR_REG, addr);
231 WR4(sc, CR_REG, val);
232 WR4(sc, ISR_REG, RD4(sc, ISR_REG));
233 WR4(sc, TRANS_SIZE_REG, datalen)
[all...] |
| dwc_wdt.c | 86 #define WR4(sc, reg, val) \
116 WR4(sc, WDT_CRR, crr);
142 WR4(sc, WDT_TORR, torr);
147 WR4(sc, WDT_CR, cr);
|
| /src/sys/arch/evbppc/nintendo/ |
| pic_pi.c | 65 #define WR4(reg, val) out32(reg, val)
92 WR4(pic_s[cpu_num].intmr, pic_s[cpu_num].irqmask & ~pic_s[cpu_num].actmask);
101 WR4(pic_s[cpu_num].intmr, pic_s[cpu_num].irqmask & ~pic_s[cpu_num].actmask);
141 WR4(pic_s[cpu_num].intmr, pic_s[cpu_num].irqmask & ~pic_s[cpu_num].actmask);
152 WR4(pic_s[cpu_num].intmr, pic_s[cpu_num].irqmask & ~pic_s[cpu_num].actmask);
153 WR4(pic_s[cpu_num].intsr, __BIT(irq));
185 WR4(pic_s[cpu_num].intmr, 0);
186 WR4(pic_s[cpu_num].intsr, ~0U);
|
| /src/sys/arch/arm/rockchip/ |
| rk_i2c.c | 126 #define WR4(sc, reg, val) \
154 WR4(sc, RKI2C_CLKDIV,
161 WR4(sc, RKI2C_CON, 0);
162 WR4(sc, RKI2C_IEN, 0);
163 WR4(sc, RKI2C_IPD, RD4(sc, RKI2C_IPD));
180 WR4(sc, RKI2C_IPD, val & ipdmask);
199 WR4(sc, RKI2C_CON, con);
205 WR4(sc, RKI2C_CON, con);
219 WR4(sc, RKI2C_CON, con);
225 WR4(sc, RKI2C_CON, con)
[all...] |
| rk_emmcphy.c | 105 #define WR4(sc, reg, val) \
146 WR4(sc, GRF_EMMCPHY_CON6, (mask << 16) | val);
151 WR4(sc, GRF_EMMCPHY_CON0, (mask << 16) | val);
157 WR4(sc, GRF_EMMCPHY_CON6, (mask << 16) | val);
184 WR4(sc, GRF_EMMCPHY_CON6, (mask << 16) | val);
198 WR4(sc, GRF_EMMCPHY_CON0, (mask << 16) | val);
203 WR4(sc, GRF_EMMCPHY_CON6, (mask << 16) | val);
|
| rk_vop.c | 186 #define WR4(sc, reg, val) \
194 WR4(sc, reg, ((uint32_t)mask << 16) | val);
248 WR4(sc, VOP_DSP_CTRL1, val);
258 WR4(sc, VOP_SYS_CTRL, val);
325 WR4(sc, VOP_WIN0_ACT_INFO, val);
331 WR4(sc, VOP_WIN0_DSP_INFO, val);
339 WR4(sc, VOP_WIN0_DSP_ST, val);
341 WR4(sc, VOP_WIN0_COLOR_KEY, 0);
354 WR4(sc, VOP_WIN0_CTRL, val);
374 WR4(sc, VOP_WIN0_VIR, val)
[all...] |
| /src/sys/arch/arm/ti/ |
| ti_wdt.c | 90 #define WR4(sc, reg, val) \
123 WR4(sc, WDT_WDSC, val);
137 WR4(sc, WDT_WSPR, 0xaaaa);
139 WR4(sc, WDT_WSPR, 0x5555);
146 WR4(sc, WDT_WSPR, 0xbbbb);
148 WR4(sc, WDT_WSPR, 0x4444);
176 WR4(sc, WDT_WCLR, WCLR_PRE | __SHIFTIN(1, WCLR_PTV));
177 WR4(sc, WDT_WLDR, counter_val);
178 WR4(sc, WDT_WCRR, counter_val);
195 WR4(sc, WDT_WTGR, ~val)
[all...] |
| ti_rng.c | 66 #define WR4(sc, reg, val) \
104 WR4(sc, TRNG_CONFIG_REG,
107 WR4(sc, TRNG_CONTROL_REG,
137 WR4(sc, TRNG_INTACK_REG, TRNG_INTACK_READY);
|
| ti_usbtll.c | 99 #define WR4(sc, reg, val) \
122 WR4(sc, USBTLL_CHANNEL_CONF(port), val);
131 WR4(sc, USBTLL_SYSCONFIG, USBTLL_SYSCONFIG_SOFTRESET);
153 WR4(sc, USBTLL_SYSCONFIG, val);
159 WR4(sc, USBTLL_SHARED_CONF, val);
|
| ti_gpio.c | 141 #define WR4(sc, reg, val) \
162 WR4(sc, GPIO_OE, oe);
254 WR4(sc, data_reg, data_mask);
274 WR4(sc, GPIO_IRQENABLE1, val & ~pin_mask);
276 WR4(sc, GPIO_IRQENABLE1_CLR, pin_mask);
327 WR4(sc, GPIO_LEVELDETECT0, val);
334 WR4(sc, GPIO_LEVELDETECT1, val);
341 WR4(sc, GPIO_RISINGDETECT, val);
348 WR4(sc, GPIO_FALLINGDETECT, val);
353 WR4(sc, GPIO_IRQENABLE1, val | pin_mask)
[all...] |
| ti_omaptimer.c | 117 #define WR4(sc, reg, val) \
128 WR4(sc, TIMER_TISR, OVF_IT_FLAG);
152 WR4(sc, TIMER_TIER, OVF_EN_FLAG);
167 WR4(sc, TIMER_TLDR, value);
168 WR4(sc, TIMER_TCRR, value);
169 WR4(sc, TIMER_TIER, 0);
170 WR4(sc, TIMER_TCLR, TCLR_ST | TCLR_AR);
|
| /src/sys/arch/riscv/starfive/ |
| jh7110_trng.c | 64 #define WR4(sc, reg, val) \
146 #define WR4(sc, reg, val) \
153 WR4(sc, JH7110_TRNG_IENABLE,
163 WR4(sc, JH7110_TRNG_IENABLE, 0);
178 WR4(sc, JH7110_TRNG_ISTATUS,
200 WR4(sc, JH7110_TRNG_CTRL,
206 WR4(sc, JH7110_TRNG_CTRL,
252 WR4(sc, JH7110_TRNG_ISTATUS, istat);
267 WR4(sc, JH7110_TRNG_IENABLE, 0U);
268 WR4(sc, JH7110_TRNG_ISTATUS, ~0U)
[all...] |
| jh71x0_temp.c | 53 #define WR4(sc, reg, val) \
92 WR4(sc, JH71X0_TEMP, JH71X0_TEMP_PD);
96 WR4(sc, JH71X0_TEMP, 0);
100 WR4(sc, JH71X0_TEMP, JH71X0_TEMP_RSTN);
104 WR4(sc, JH71X0_TEMP, JH71X0_TEMP_RSTN | JH71X0_TEMP_RUN);
|
| jh7110_pcie.c | 81 #define WR4(sc, reg, val) \
85 WR4((sc), (off), RD4((sc), (off)) | (mask))
87 WR4((sc), (off), RD4((sc), (off)) & ~(mask))
89 WR4((sc), (off), (RD4((sc), (off)) & ~(clr)) | (set))
371 WR4(sc, PLDA_ISTATUS_LOCAL, status);
516 WR4(sc, PLDA_ATR_AXI4_SLV0_SRC_ADDR_LO(0),
520 WR4(sc, PLDA_ATR_AXI4_SLV0_SRC_ADDR_HI(0), BUS_ADDR_HI32(sc->sc_cfg_addr));
521 WR4(sc, PLDA_ATR_AXI4_SLV0_TRSL_ADDR_LO(0), 0);
522 WR4(sc, PLDA_ATR_AXI4_SLV0_TRSL_ADDR_HI(0), 0);
523 WR4(sc, PLDA_ATR_AXI4_SLV0_TRSL_PARAM(0), PLDA_TRSL_ID_PCIE_CONFIG)
[all...] |
| jh7110_pciephy.c | 59 #define WR4(sc, reg, val) \
137 WR4(sc, PCIE_KVCO_LEVEL, PCEI_PHY_KVCO_FINE_TUNE_LEVEL);
138 WR4(sc, PCIE_KVCO_TUNE_SIGNAL, PCIE_KVO_FINE_TUNE_SIGNALS);
|
| /src/sys/arch/arm/sunxi/ |
| sun8i_codec.c | 131 #define WR4(sc, reg, val) \
263 WR4(sc, AIF1CLK_CTRL, val);
295 WR4(sc, HMIC_CTRL1, val);
349 WR4(sc, HMIC_STS, val);
427 WR4(sc, SYSCLK_CTL, val);
428 WR4(sc, MOD_CLK_ENA, MOD_AIF1 | MOD_ADC | MOD_DAC);
429 WR4(sc, MOD_RST_CTL, MOD_AIF1 | MOD_ADC | MOD_DAC);
432 WR4(sc, DAC_DIG_CTRL, DAC_DIG_CTRL_ENDA);
433 WR4(sc, ADC_DIG_CTRL, ADC_DIG_CTRL_ENAD);
439 WR4(sc, SYS_SR_CTRL, val)
[all...] |
| /src/sys/dev/fdt/ |
| dwc3_fdt.c | 92 #define WR4(sc, reg, val) \
95 WR4((sc), (reg), RD4((sc), (reg)) | (mask))
97 WR4((sc), (reg), RD4((sc), (reg)) & ~(mask))
158 WR4(sc, DWC3_GUSB2PHYCFG(0), val);
166 WR4(sc, DWC3_GUSB3PIPECTL(0), val);
172 WR4(sc, DWC3_GUCTL1, val);
191 WR4(sc, DWC3_DCFG, val);
202 WR4(sc, DWC3_GCTL, val);
|
